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View Code? Open in Web Editor NEWAXI interface modules for Cocotb
License: MIT License
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There aren't examples about AxiSlave, AxiLiteSlave, or from_entity
Probably are there also other useful examples missing, but these are what I am interested in. I searched under verilog-axi/tb and cocotbext-tests:
grep -r AxiSlave verilog-axi/tb
grep -r AxiLiteSlave verilog-axi/tb
grep -r from_entity verilog-axi/tb
grep -r AxiSlave cocotbext-axi/tests/
grep -r AxiLiteSlave cocotbext-axi/tests/
grep -r from_entity cocotbext-axi/tests/
I know now that you can use .from_entity(dut) when you haven't a prefix.
I can't install cocotbext-axi - please help
I tried the following but I am still getting the same error
hossam@hossam:~/Projects$ git clone https://github.com/alexforencich/cocotbext-axi`
hossam@hossam:~/Projects$ pip install -e cocotbext-axi
Obtaining file:///home/hossam/Projects/cocotbext-axi
Complete output from command python setup.py egg_info:
Traceback (most recent call last):
File "<string>", line 1, in <module>
File "/home/hossam/Projects/cocotbext-axi/setup.py", line 2, in <module>
setup()
File "/usr/lib/python2.7/dist-packages/setuptools/__init__.py", line 129, in setup
return distutils.core.setup(**attrs)
File "/usr/lib/python2.7/distutils/core.py", line 124, in setup
dist.parse_config_files()
File "/usr/lib/python2.7/dist-packages/setuptools/dist.py", line 494, in parse_config_files
ignore_option_errors=ignore_option_errors)
File "/usr/lib/python2.7/dist-packages/setuptools/config.py", line 106, in parse_configuration
meta.parse()
File "/usr/lib/python2.7/dist-packages/setuptools/config.py", line 382, in parse
section_parser_method(section_options)
File "/usr/lib/python2.7/dist-packages/setuptools/config.py", line 355, in parse_section
self[name] = value
File "/usr/lib/python2.7/dist-packages/setuptools/config.py", line 173, in __setitem__
value = parser(value)
File "/usr/lib/python2.7/dist-packages/setuptools/config.py", line 430, in _parse_version
version = self._parse_attr(value)
File "/usr/lib/python2.7/dist-packages/setuptools/config.py", line 305, in _parse_attr
module = import_module(module_name)
File "/usr/lib/python2.7/importlib/__init__.py", line 37, in import_module
__import__(name)
ImportError: No module named cocotbext.axi.version
----------------------------------------
Command "python setup.py egg_info" failed with error code 1 in /home/hossam/Projects/cocotbext-axi/`
Any help will be appreciated.
idle_ and backpressure_ inserters not working in test_axis.py
Hi,
Great work!
I'm new to cocotb so sorry if I'm missing something obvious, but are the idle_ and backpressure_inserters (a.k.a. pause_generators) working in test_axis.py ?
I'm running the latest cocotb with the makefile-flow.
I expected the idles/backpressure to produce variation in the periodicity of the tvalid and tready signals but these signals appear "regular as clockwork" (?)
AxiStreamFrame assumes byte width 1 without TKEEP. Expected: self.width / 8 as default.
If I connect a AXIS source to an AXIS sink, without (the optional) TKEEP, the self.byte_lanes is incorrectly 1 rather than all lanes enabled.
self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "sink"), dut.clk, dut.reset)
Root cause is AxiStreamFrame assumes byte width 1 if optional TKEEP[] is not present, but it should default to self.width // 8 because the AXIS specification mentions "when TKEEP is absent, TKEEP defaults to all bits HIGH" and "The width of the data payload is an integer number of bytes."
Fix: https://github.com/alexforencich/cocotbext-axi/blob/master/cocotbext/axi/axis.py#L290
- self.byte_lanes = 1
+ self.byte_lanes = self.width // 8
I will also put a pull request on GitHub: #47
AxiStreamMonitor / AxiStreamSink: idle() not working as expected
While working with the AxiStreamMonitor / AxiStreamSink classes, I had the impression that the function 'def idle(self)' of these classes does not work as expected. I want to use it, to check if the bus is idle, all packets have arrived and the test can be terminated.
The function is based on the self.active variable, but I have not found a situation when it would be set to true.
Did I miss something?
Thank you
AxiLiteMaster reads forever
I wrote a simple test for a slave. It has a register with a hard-coded version number (1).
The source code is in VHDL.
The master's read operation never ends.
import cocotb
from cocotb.clock import Clock
from cocotbext.axi import AxiLiteBus, AxiLiteMaster
PERIOD = 8 # ns
@cocotb.test()
async def test_axi_read_version(dut):
"""Version test"""
clk = dut.s00_axi_aclk
rst = dut.s00_axi_aresetn
cocotb.start_soon(Clock(clk, period=PERIOD, units="ns").start())
bus = AxiLiteBus.from_prefix(dut, "s00_axi")
master = AxiLiteMaster(bus, clk, rst)
version = await master.read(0x000c, 1)
assert version.data == b'1', f"The version {version.data} is not 1."This is my console output:
/usr/local/bin/ghdl -i --workdir=sim_build --work=work /workspaces/MSE-Tesis/fpga/test/axi_data_generator/../../src/data_generator.vhdl /workspaces/MSE-Tesis/fpga/test/axi_data_generator/../../src/axi_data_generator_v1_0_AXI.vhd /workspaces/MSE-Tesis/fpga/test/axi_data_generator/../../src/axi_data_generator_v1_0.vhd && \
/usr/local/bin/ghdl -m --workdir=sim_build -Psim_build --work=work axi_data_generator_v1_0
/workspaces/MSE-Tesis/fpga/test/axi_data_generator/../../src/axi_data_generator_v1_0_AXI.vhd:248:33:warning: declaration of "byte_index" hides signal "byte_index" [-Whide]
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8 - 1) LOOP
^
/workspaces/MSE-Tesis/fpga/test/axi_data_generator/../../src/axi_data_generator_v1_0_AXI.vhd:256:33:warning: declaration of "byte_index" hides signal "byte_index" [-Whide]
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8 - 1) LOOP
^
/workspaces/MSE-Tesis/fpga/test/axi_data_generator/../../src/axi_data_generator_v1_0_AXI.vhd:264:33:warning: declaration of "byte_index" hides signal "byte_index" [-Whide]
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8 - 1) LOOP
^
/workspaces/MSE-Tesis/fpga/test/axi_data_generator/../../src/axi_data_generator_v1_0_AXI.vhd:272:33:warning: declaration of "byte_index" hides signal "byte_index" [-Whide]
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8 - 1) LOOP
^
../../src/ieee/math_real-body.vhdl:830:14:warning: declaration of "real_vector" hides type "real_vector" [-Whide]
type REAL_VECTOR is array (NATURAL range <>) of REAL;
^
analyze /workspaces/MSE-Tesis/fpga/test/axi_data_generator/../../src/axi_data_generator_v1_0.vhd
analyze /workspaces/MSE-Tesis/fpga/test/axi_data_generator/../../src/axi_data_generator_v1_0_AXI.vhd
/workspaces/MSE-Tesis/fpga/test/axi_data_generator/../../src/axi_data_generator_v1_0_AXI.vhd:248:33:warning: declaration of "byte_index" hides signal "byte_index" [-Whide]
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8 - 1) LOOP
^
/workspaces/MSE-Tesis/fpga/test/axi_data_generator/../../src/axi_data_generator_v1_0_AXI.vhd:256:33:warning: declaration of "byte_index" hides signal "byte_index" [-Whide]
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8 - 1) LOOP
^
/workspaces/MSE-Tesis/fpga/test/axi_data_generator/../../src/axi_data_generator_v1_0_AXI.vhd:264:33:warning: declaration of "byte_index" hides signal "byte_index" [-Whide]
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8 - 1) LOOP
^
/workspaces/MSE-Tesis/fpga/test/axi_data_generator/../../src/axi_data_generator_v1_0_AXI.vhd:272:33:warning: declaration of "byte_index" hides signal "byte_index" [-Whide]
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8 - 1) LOOP
^
analyze /workspaces/MSE-Tesis/fpga/test/axi_data_generator/../../src/data_generator.vhdl
elaborate axi_data_generator_v1_0
rm -f results.xml
MODULE=test_axi_data_generator TESTCASE= TOPLEVEL=axi_data_generator_v1_0 TOPLEVEL_LANG=vhdl \
/usr/local/bin/ghdl -r --workdir=sim_build -Psim_build --work=work axi_data_generator_v1_0 --vpi=/usr/local/lib/python3.9/dist-packages/cocotb/libs/libcocotbvpi_ghdl.so --vcd=axi_data_generator_v1_0.vcd
loading VPI module '/usr/local/lib/python3.9/dist-packages/cocotb/libs/libcocotbvpi_ghdl.so'
-.--ns INFO gpi ..mbed/gpi_embed.cpp:76 in set_program_name_in_venv Did not detect Python virtual environment. Using system-wide Python interpreter
-.--ns INFO gpi ../gpi/GpiCommon.cpp:101 in gpi_print_registered_impl VPI registered
VPI module loaded!
0.00ns INFO cocotb Running on GHDL version 3.0.0-dev (v2.0.0-952-gd908ceeed) [Dunoon edition]
0.00ns INFO cocotb Running tests with cocotb v1.8.0.dev0 from /usr/local/lib/python3.9/dist-packages/cocotb
0.00ns INFO cocotb Seeding Python random module with 1672608203
0.00ns INFO cocotb.regression Found test test_axi_data_generator.test_axi_read_version
0.00ns INFO cocotb.regression running test_axi_read_version (1/1)
Testing the
vpi_get_str: unhandled property
vpi_get_str: unhandled property
0.00ns INFO ...axi_data_generator_v1_0.s00_axi AXI lite master (write)
0.00ns INFO ...axi_data_generator_v1_0.s00_axi cocotbext-axi version 0.1.18
0.00ns INFO ...axi_data_generator_v1_0.s00_axi Copyright (c) 2020 Alex Forencich
0.00ns INFO ...axi_data_generator_v1_0.s00_axi https://github.com/alexforencich/cocotbext-axi
0.00ns INFO ...axi_data_generator_v1_0.s00_axi Reset de-asserted
0.00ns INFO ...axi_data_generator_v1_0.s00_axi Reset de-asserted
0.00ns INFO ...axi_data_generator_v1_0.s00_axi Reset de-asserted
0.00ns INFO ...axi_data_generator_v1_0.s00_axi AXI lite master configuration:
0.00ns INFO ...axi_data_generator_v1_0.s00_axi Address width: 4 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi Byte size: 8 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi Data width: 32 bits (4 bytes)
0.00ns INFO ...axi_data_generator_v1_0.s00_axi AXI lite master signals:
0.00ns INFO ...axi_data_generator_v1_0.s00_axi awaddr width: 4 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi awprot width: 3 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi awready width: 1 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi awvalid width: 1 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi wdata width: 32 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi wready width: 1 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi wstrb width: 4 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi wvalid width: 1 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi bready width: 1 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi bresp width: 2 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi bvalid width: 1 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi Reset de-asserted
0.00ns INFO ...axi_data_generator_v1_0.s00_axi AXI lite master (read)
0.00ns INFO ...axi_data_generator_v1_0.s00_axi cocotbext-axi version 0.1.18
0.00ns INFO ...axi_data_generator_v1_0.s00_axi Copyright (c) 2020 Alex Forencich
0.00ns INFO ...axi_data_generator_v1_0.s00_axi https://github.com/alexforencich/cocotbext-axi
0.00ns INFO ...axi_data_generator_v1_0.s00_axi Reset de-asserted
0.00ns INFO ...axi_data_generator_v1_0.s00_axi Reset de-asserted
0.00ns INFO ...axi_data_generator_v1_0.s00_axi AXI lite master configuration:
0.00ns INFO ...axi_data_generator_v1_0.s00_axi Address width: 4 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi Byte size: 8 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi Data width: 32 bits (4 bytes)
0.00ns INFO ...axi_data_generator_v1_0.s00_axi AXI lite master signals:
0.00ns INFO ...axi_data_generator_v1_0.s00_axi araddr width: 4 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi arprot width: 3 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi arready width: 1 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi arvalid width: 1 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi rdata width: 32 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi rready width: 1 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi rresp width: 2 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi rvalid width: 1 bits
0.00ns INFO ...axi_data_generator_v1_0.s00_axi Reset de-asserted
0.00ns INFO ...axi_data_generator_v1_0.s00_axi Read start addr: 0x0000000c prot: AxiProt.NONSECURE length: 1AXIStream: self.width = len(self.bus.tdata) TypeError: object of type 'NoneType' has no len()
cocotb=1.6.2
cocotbext-axi = 0.1.16
Active HDL 11.1
When I define an
axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "bfm_m_axis"), dut.clk_in, dut.reset)
and axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "bfm_s_axis"), dut.clk_in, dut.reset)
I get the error self.width = len(self.bus.tdata) TypeError: object of type 'NoneType' has no len() on the axis_sink.
Here is my entity:
port(
clk_in : in std_logic := '0';
reset : in std_logic := '0';
bfm_m_axis_tdata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
bfm_m_axis_tvalid : in std_logic := '0';
bfm_m_axis_tid : in std_logic_vector(ID_WIDTH-1 downto 0) := (others => '0');
bfm_m_axis_tdest : in std_logic_vector(DEST_WIDTH-1 downto 0):= (others => '0');
bfm_s_axis_tready : in std_logic := '0';
bfm_s_axis_tdata : out std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
bfm_s_axis_tvalid : out std_logic := '0';
bfm_s_axis_tid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others => '0');
bfm_s_axis_tdest : out std_logic_vector(DEST_WIDTH-1 downto 0):= (others => '0');
bfm_m_axis_tready : out std_logic := '0'
);
end entity;
However, if I remove either the source or sink object then remove the corresponding signals in the entity it runs fine.
Byte swap
First of all thanks for making this cocotb extension available.
I've written a simple testbench using AxiStreamSource and AxiStreamSink, which is working well.
Only thing I'm currently missing is the ability to do byte swapping when writing/reading data to/from the DUT.
I've worked around the issue by using a HDL wrapper module with byte swapping applied at input and output of the DUT. However, would be great if byte swapping could be supported directly by the cocotb AXI modules to avoid extra work writing HDL wrapper modules.
Thanks!
Question - does it support array of I/Fs?
Hi,
is there a way to specify an array index when creating the bus? Something like...
axim_0 = AXI4Master(dut, AXI_PREFIX, dut.clk, index_array=0)
Logging TX frame and RX frame
Logging TX frames and RX frames in axis.py would be much nicer using self.log.debug instead of self.log.info.
Cocotb v1.6: DeprecationWarning
With cocotb v1.6 the use of <= syntax is deprecated. As the cocotbext-axi packet makes use of this syntax, several warnings are shown for each interface.
DeprecationWarning: Setting values on handles using the
handle <= valuesyntax is deprecated. Instead use thehandle.value = valuesyntax
In order to keep my logs as warning/error free as possible, I would appreciate it, if this could be changed.
I created a PR addressing this issue.
Thank you
Resets with active low logic level
I believe that the current implementation only supports active high reset implementations. In an active low case the simulation seems to stall in the reset section. I think a parameter should be introduced that specifies the reset polarity so that both cases work depending on the configuration.
I wanted to discuss this issue before jumping the gun and creating a pull-request. What are your thoughts?
simulator hangs
- environment: cocotb 1.7.1 questasim
- req_sink is AxisStreamSink, resp_source is AxisStreamSource
- I want to use socket to communication with external server, simulator hangs. Below is the code snippet:
async def _tx(self):
while True:
pkt = await self.req_sink.recv()
self.client.send(pkt.tdata)
async def _rx(self):
while True:
pkt = self.client.recv(1024)
await self.resp_source.send(pkt)
def start(self):
self.client = socket.socket()
self.client.connect(('127.0.0.1',8000))
self.tx_thread = cocotb.start_soon(self._tx())
self.rx_thread = cocotb.start_soon(self._rx())Cocotb Scorebord
Hello Alex
First: Thank you for your great work!
Is there a possibility to use the cocotb scorebord with this driver? (I try to use the AxiStream Monitor)
If not, are there plans to implement this?
Thank you
Silvan
Axis DUT signal naming
Hi,
The SystemVerilog / Verilog standard I use requires _i or _o at the end of port names. For example:
input logic [DATA_WIDTH-1:0] axis_tdata_i,
input logic axis_tvalid_i,
output logic axis_tready_o,
I see you have the from_prefix to facilitate signal matching for the front end of the signal name. Is there a way to match the backend _i _o also?
Thanks
David
Using custom signal names
Hi,
is there a way I'm overlooking to use custom signal names during bus creation (for StreamBus for example)?
Small bugs at axi_slave.py
Hello,
I initialise an AxiRam with:
mem = AxiRam(AxiBus.from_prefix(dut, 'm_axi'), dut.clk, size=RAM_SIZE)
In the "axi_slave.py" file at lines 114 & 274, the awid and arid signals cannot be resolved:
- ValueError: Unresolvable bit in binary string: 'U'
I have fixed that by setting at the beginning of my testbench "dut.m_axi_arid.value = 0" and "dut.m_axi_awid.value = 0". I thought it would be done automatically during the initialisation of the AxiRam.
Also at lines 119 & 279 I had to add an int() to make it work:
line 119: prot = AxiProt(int(getattr(aw, 'awprot', AxiProt.NONSECURE)))
line 279: prot = AxiProt(int(getattr(ar, 'arprot', AxiProt.NONSECURE)))
Uppercase signals are not supported
Is not uncommon to have the AXI signals written in uppercase, as in the spec. But if you specify an AXI signal in this way:
1.00ns INFO test_master failed
Traceback (most recent call last):
File "/home/rodrigo/repos/0thers-axi/cocotbext-axi/tests/axil/test_axil.py", line 6, in test_master
axil_mst = AxiLiteMaster(AxiLiteBus.from_prefix(dut, 'axil'), dut.clk, dut.rst)
File "/usr/local/lib/python3.8/dist-packages/cocotbext/axi/axil_channels.py", line 122, in from_prefix
write = AxiLiteWriteBus.from_prefix(entity, prefix, **kwargs)
File "/usr/local/lib/python3.8/dist-packages/cocotbext/axi/axil_channels.py", line 77, in from_prefix
aw = AxiLiteAWBus.from_prefix(entity, prefix, **kwargs)
File "/usr/local/lib/python3.8/dist-packages/cocotbext/axi/stream.py", line 49, in from_prefix
return cls(entity, prefix, **kwargs)
File "/usr/local/lib/python3.8/dist-packages/cocotbext/axi/stream.py", line 41, in __init__
super().__init__(entity, prefix, self._signals, optional_signals=self._optional_signals, **kwargs)
File "/usr/local/lib/python3.8/dist-packages/cocotb_bus/bus.py", line 62, in __init__
self._add_signal(attr_name, signame, array_idx)
File "/usr/local/lib/python3.8/dist-packages/cocotb_bus/bus.py", line 79, in _add_signal
handle = getattr(self._entity, signame)
File "/usr/local/lib/python3.8/dist-packages/cocotb/handle.py", line 346, in __getattr__
raise AttributeError(f"{self._name} contains no object named {name}")
AttributeError: test_axil contains no object named axil_awaddr
I see that cocotb/handle.py is not finding the signal, but maybe a "magic" could be performed in the cocotbext-axi side? Or do you have a workaround to recommend me?
AxiMaster overloads cocotb scheduler when using large AXI-ID vectors
AxiMaster schedules ~2**(id_length+1) coroutines upon its creation. This slows down simulation considerably.
at 17 bits width:
INFO cocotb:simulator.py:289 # 412.00ns INFO cocotb.regression regression.py:574 in _log_sim_summary *************************************************************************************
INFO cocotb:simulator.py:289 # ** ERRORS : 0 **
INFO cocotb:simulator.py:289 # *************************************************************************************
INFO cocotb:simulator.py:289 # ** SIM TIME : 412.00 NS **
INFO cocotb:simulator.py:289 # ** REAL TIME : 36.39 S **
INFO cocotb:simulator.py:289 # ** SIM / REAL TIME : 11.32 NS/S **
INFO cocotb:simulator.py:289 # *************************************************************************************
INFO cocotb:simulator.py:289 #
INFO cocotb:simulator.py:289 # 412.00ns INFO cocotb.regression regression.py:259 in tear_down Shutting down...
INFO cocotb:simulator.py:289 # Simulation halt requested by foreign interface.
Profiling graph:
AXILiteMaster incorrect write data
My code is
@cocotb.test()
async def my_first_test(dut):
"""Try accessing the design."""
dut._log.info("Running test!")
axi_master = AxiLiteMaster(dut, "axi_slave", dut.CLK)
cocotb.fork(Clock(dut.CLK, 1250, 'ps').start())
dut._log.info("Running test!")
await axi_master.write(0x800,0x04)
data=await axi_master.read(0x800,4)
dut._log.info("Read "+repr(data))
When I simulate this i expected to see 4 on the wdata bus but I am seeing 0.
I put a few print statements to debug this...
axil_master
async def write(self, address, data, prot=AxiProt.NONSECURE):
¦ event = Event()
¦ cocotb.log.warn("Write Data is "+repr(data))
shows "WARNING Write Data is 4 "
In async def _process_write(self)
¦ ¦ cmd = self.write_command_queue.popleft()
¦ ¦ self.log.info("cmd="+repr(cmd))
I see cmd=AxiLiteWriteCmd(address=2048, data=bytearray(b'\x00\x00\x00\x00'), prot=170, event=<Event at 0x7f2af9c580a0>)
Am I doing something wrong? Or is the axilite module broken?
[Question] Handling array of structs with bus drivers
Hey @alexforencich,
thanks for the repository, I still didn't have time to implement it but I went through it shortly and it's really amazing. Sorry for raising this issue but didn't know a better way to ask you this question but do you have an idea of how to connect your AXIMaster bus drivers for an AXI slave that's an array of structs and it has different names for miso/mosi signals?
SV Structs:
simengine: verilator-master
Thanks!
AttributeError: 'NoneType' object has no attribute 'setimmediatevalue'
cocotbext-axi==0.1.16
Hello,
I am trying to drive my AXI4-Lite slave with this master:
self.axi_drv = AxiLiteMaster(AxiLiteBus.from_prefix(self.dut, "AXI4_LITE_"), self.dut.i_clk, self.dut.i_rst_n)
but have an error in Questa when execution PY script:
self.axi_drv = AxiLiteMaster(AxiLiteBus.from_prefix(self.dut, "AXI4_LITE_"), self.dut.i_clk, self.dut.i_rst_n)
File "/usr/local/lib/python3.6/site-packages/cocotbext/axi/axil_master.py", line 521, in __init__
self.write_if = AxiLiteMasterWrite(bus.write, clock, reset, reset_active_level, **kwargs)
File "/usr/local/lib/python3.6/site-packages/cocotbext/axi/axil_master.py", line 98, in __init__
self.aw_channel = AxiLiteAWSource(bus.aw, clock, reset, reset_active_level)
File "/usr/local/lib/python3.6/site-packages/cocotbext/axi/stream.py", line 197, in __init__
super().__init__(bus, clock, reset, reset_active_level, *args, **kwargs)
File "/usr/local/lib/python3.6/site-packages/cocotbext/axi/stream.py", line 114, in __init__
self.valid.setimmediatevalue(self._valid_init)
AttributeError: 'NoneType' object has no attribute 'setimmediatevalue'
Does anybody know the solution?
axi address width causing overflow
hi, I tried to connect AxiRam with axi interface which has 64 bit addr width...but it resulted into overflow error in C...is this addr size not support in cocotb axi at the moment?
Manually set a bus signal as optional even if present
Hi, this is a usecase I believe may be useful to have for SystemVerilog interfaces. Some designs have an interface that defines many signals, but with modules that may not be using all of those signals. An example below is a AXI Stream interface with tdata and tid, but with a module that does not assign tid.
Since tid is present on the bus, AxiStreamSink will try to resolve the value to an integer which won't work because it remains at 'x'. Would it make sense to have a way to specify that a signal should not be used/resolved for such cases?
Module:
interface axis_if #(
parameter int DATA_WIDTH = 8,
parameter int ID_WIDTH = 2
);
logic tvalid;
logic tready;
logic [DATA_WIDTH-1:0] tdata;
logic [ID_WIDTH-1:0] tid;
endinterface
module top;
logic clk;
axis_if axis ();
assign axis.tvalid = '1;
assign axis.tdata = '1;
endmoduleTestcase:
import cocotb
from cocotb.clock import Clock
from cocotbext.axi import AxiStreamBus, AxiStreamSink
@cocotb.test()
async def test_top(dut):
cocotb.start_soon(Clock(dut.clk, 1, units="ns").start())
receiver = AxiStreamSink(AxiStreamBus.from_entity(dut.axis), dut.clk)
frame = await receiver.recv()Log:
0.00ns INFO cocotb Running on ModelSim for QuestaIntel FPGA Edition-64 version 2022.1 2022.01
0.00ns INFO cocotb Running tests with cocotb v1.7.2 from /home/user/venv/lib64/python3.11/site-packages/cocotb
0.00ns INFO cocotb Seeding Python random module with 1673369237
0.00ns INFO cocotb.regression Found test test_top.test_top
0.00ns INFO cocotb.regression running test_top (1/1)
0.00ns INFO cocotb.axis.None AXI stream sink
0.00ns INFO cocotb.axis.None cocotbext-axi version 0.1.18
0.00ns INFO cocotb.axis.None Copyright (c) 2020 Alex Forencich
0.00ns INFO cocotb.axis.None https://github.com/alexforencich/cocotbext-axi
0.00ns INFO cocotb.axis.None AXI stream sink configuration:
0.00ns INFO cocotb.axis.None Byte size: 8 bits
0.00ns INFO cocotb.axis.None Data width: 8 bits (1 bytes)
0.00ns INFO cocotb.axis.None AXI stream sink signals:
0.00ns INFO cocotb.axis.None tdata width: 8 bits
0.00ns INFO cocotb.axis.None tdest: not present
0.00ns INFO cocotb.axis.None tid width: 2 bits
0.00ns INFO cocotb.axis.None tkeep: not present
0.00ns INFO cocotb.axis.None tlast: not present
0.00ns INFO cocotb.axis.None tready width: 1 bits
0.00ns INFO cocotb.axis.None tuser: not present
0.00ns INFO cocotb.axis.None tvalid width: 1 bits
0.00ns INFO cocotb.axis.None Reset de-asserted
1.00ns ERROR cocotb.Task 1.AxiStreamSink._run Exception raised by this forked coroutine
1.00ns INFO cocotb.regression test_top failed
Traceback (most recent call last):
File "/home/user/venv/lib64/python3.11/site-packages/cocotbext/axi/axis.py", line 725, in _run
frame.tid.append(self.bus.tid.value.integer)
^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/home/user/venv/lib64/python3.11/site-packages/cocotb/binary.py", line 372, in integer
return self._convert_from(self._str)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/home/user/venv/lib64/python3.11/site-packages/cocotb/binary.py", line 252, in _convert_from_unsigned
return int(x.translate(_resolve_table), 2)
^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/home/user/venv/lib64/python3.11/site-packages/cocotb/binary.py", line 84, in __missing__
return self.resolve_x(key)
^^^^^^^^^^^^^^^^^^^
File "/home/user/venv/lib64/python3.11/site-packages/cocotb/binary.py", line 61, in resolve_error
raise ValueError(
ValueError: Unresolvable bit in binary string: 'x'
1.00ns INFO cocotb.regression **************************************************************************************
** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) **
**************************************************************************************
** test_top.test_top FAIL 1.00 0.03 37.45 **
**************************************************************************************
** TESTS=1 PASS=0 FAIL=1 SKIP=0 1.00 0.18 5.51 **
**************************************************************************************
Make Verilator faster?
Just a suggestion.
Verilator seems to work but can easily be made faster:
- change timescale in Verilog top to
timescale 1ns / 1ns(this will be one clock tick/ns) - use fasted possible clock in this case 2ns period
cocotb.fork(Clock(dut.clk, 2, units="ns").start())(no clock ticks that nothing is going on)
Read fails if signal has length of 0
In my design, the AxiStream bus is packed into an record. Unused signals are define with a length of 0. When unpacking the record and feeding it to cocoTB and your driver the simulations fail:
The check if a signal exists returns True (if hasattr(self.bus, "tuser"):) but the signal can not be converted into an integer
(frame.tuser.append(self.bus.tuser.value.integer)). This fails as the signal with length 0 can not be converted.
I quickfixed this by the code below and was able to make the simulation run:
if hasattr(self.bus, "tuser") and self.bus.tuser.value._n_bits != 0:
I'm sure there are much better solutions to address this issue.
my Tb_wrapper.vhd
generic(dataByte : positive := 8;
HasTkeep : natural := 1;
HasTstrb : natural := 0;
idLength : natural := 0;
userLength : natural := 0;
......
);
port(
Clk : in std_logic;
Rst : in std_logic;
S0_Tvalid : in std_logic;
S0_Tdata : in std_logic_vector(dataByte * 8 - 1 downto 0);
S0_Tstrb : in std_logic_vector(HasTstrb * dataByte - 1 downto 0);
S0_Tkeep : in std_logic_vector(HasTkeep * dataByte - 1 downto 0);
S0_Tlast : in std_logic;
S0_Tid : in std_logic_vector(idLength - 1 downto 0);
S0_Tdest : in std_logic_vector(HasTkeep * dataByte - 1 downto 0);
S0_Tuser : in std_logic_vector(userLength - 1 downto 0);
S0_Tready : out std_logic;
What I changed: axis.py (line 762)
if tready_sample and tvalid_sample:
for offset in range(self.byte_lanes):
frame.tdata.append((self.bus.tdata.value.integer >> (offset * self.byte_size)) & self.byte_mask)
if hasattr(self.bus, "tkeep"):
frame.tkeep.append((self.bus.tkeep.value.integer >> offset) & 1)
if hasattr(self.bus, "tid") and self.bus.tid.value._n_bits != 0:
frame.tid.append(self.bus.tid.value.integer)
if hasattr(self.bus, "tdest") and self.bus.tdest.value._n_bits != 0:
frame.tdest.append(self.bus.tdest.value.integer)
if hasattr(self.bus, "tuser") and self.bus.tuser.value._n_bits != 0:
frame.tuser.append(self.bus.tuser.value.integer)
How possible ot use this to replace the commercial VIP in the future?
From the documentation, seems like a very complete plan is there.
0.1.20 makes my tests fail
The tests of my complex multiplier fail, when I use version 0.1.20 instead of version 0.1.18 or lower.
https://github.com/catkira/complex_multiplier
The error log is here: https://github.com/catkira/complex_multiplier/actions/runs/4118033330/jobs/7110058904
cocotb-test dependence of the test examples
I suggest to add a note in the README that indicates that the test examples use the cocotb_test extension and that is needs to be installed to run them. Small issue that just improves the user experience.
question for install
Hello,
I am trying to run cocotbext-axi as below but I think I missed something.
% git clone https://github.com/alexforencich/cocotbext-axi
% pip install -e cocotbext-axi
% cd cocotbext-axi/tests/axi
% make
but I have below issues, would you please let me know what I missed?
File "C:\cygwin64\home\sunki\projects\examples\cocotbext-axi\tests\axi\test_axi.py", line 30, in
import cocotb_test.simulator
ModuleNotFoundError: No module named 'cocotb_test'
0.00ns ERROR cocotb.gpi gpi_embed.cpp:324 in _embed_sim_init cocotb initialization failed - exiting
0.00ns ERROR cocotb.scheduler init.py:302 in _sim_event Failing test at simulator request before test run completion: Simulator shutdown prematurely
ERROR: results.xml was not written by the simulation!
/c/users/sunki/anaconda3/lib/site-packages/cocotb/share/makefiles/simulators/Makefile.icarus:69: recipe for target 'results.xml' failed
make[1]: *** [results.xml] Error 1
make[1]: Leaving directory '/c/cygwin64/home/sunki/projects/examples/cocotbext-axi/tests/axi'
c:\users\sunki\anaconda3\lib\site-packages\cocotb\share\makefiles/Makefile.inc:39: recipe for target 'sim' failed
make: *** [sim] Error 2
Thank you in advance.
Sun Kim
AxiStreamSink cannot handle tdata X-bytes for bytes to ignore (tkeep=0)
The AxiStreamSink reads and converts tdata without respecting the tkeep bits. This can be a problem as some developers are driving tdata bits and bytes to X or U if the respective tkeep bits are low (0). This is for instance done by the Xilinx AXI4-Stream Data Width Converter when downsizing the bus and the ratio is NOT an integer multiple.
One work-around would be to set the COCOTB_RESOLVE_X environment variable to a value different from VALUE_ERROR (default). I do not like the solution though as in general I would like to see the exception if any output of a DUT that has no validity qualifier returns something else than 0 or 1.
Therefore, I convert tdata manually to 0,1 inside the top VHDL file (in my case the testbench). However, I would prefer to have this issue fixed in a future release of cocotbext-axi.
All signals except TDATA are "not present"
cocotb==1.6.2
cocotbext-axi==0.1.16
Questa Sim-64 Version 10.7f
Hello,
I am instantiate AXI-S driver like this:
self.axi4_s_drv = AxiStreamSource(AxiStreamBus.from_entity(self.dut.axi_s_if), self.dut.ACLK, self.dut.ARESETn)
I.e. TOP module contains SystemVerilog's Interface which has all required signals. Strange that TDATA is present and all the rest are missing. All other signals are in "_optional_signals" list, so may be this has something to do with the problem.
P.S. AXI4-Lite works with SV's Interfaces all-right via the same "from_entity()" method.
Axi Streaming is missing support for tstrb
The Axi-Streaming standard supports an optional tstrb component, for signalling data validity. The semantics differ from tkeep, although may be used in conjuntion with tkeep
tkeep |
tstrb |
Description |
|---|---|---|
| 0 | 0 | This byte is junk, and may be discarded from the stream |
| 1 | 0 | This is a positioning byte: it contains no information, but may not be discarded from the stream |
| 0 | 1 | An invalid bus state |
| 1 | 1 | A data byte |
An implementation is available in #60: There is at least one open question around checking the validity of tkeep / tstrb pairs.
Examples in verilog-axis
README states verilog-axis contains examples on how to use cocotbext-axi but couldn't find any testbench using cocotb at all over there. Am I blind?
Is the repo unmaintained / closed to new features?
I'm trying to ascertain the state of this repository. There are requests over 2 months old with no responses from the maintainer(s??). I'd like to understand if new features are welcome, and the maintainer is busy, or if new features are unwanted, and the PR's are ignored.
Both are fine, I understand this is open source and have no expectations on the maintainer(s) or the scope of the repo, but a statement as the the status would clarify if forking is the right way to go.
Finally, I'd be happy to act as a maintainer if desired.
AxisStreamMonitor using **kwargs results in a TypeError
I was attempting to hookup an AxiStreamMonitor to a SystemVerilog interface.
Just specifying the name of the interface obviously doesn't work because the default value of bus_separator is _ so it formats the interface signals as iface_tready instead of the (correct) iface.tready. On L251 of axis.py, **kwargs passed to the AxisMonitor.__init__() method are passed on to the Bus constructor.
Passing bus_separator='.' into the AxisMonitor constructor appears to construct the bus correctly, however **kwargs is also passed onto the parent constructor on L258 which then fails because that constructor (for Reset) takes no arguments and therefore fails with TypeError: object.__init__() takes no parameters.
Using **kwargs in both of these contexts is a bug. Either **kwargs should be passed to the Bus constructor or it should be passed to the parent constructor but not both (especially since it causes the code to crash regardless of the keyword argument that is passed). Since the parent constructor takes no arguments, I would argue that the optimal behaviour would be to pass **kwargs on to the Bus constructor (especially since this allows hooking up to SV interfaces easily, in theory).
Let me know if I've missed something here! If not, I'm making to make the PR that implements whatever changes you think are best.
All *PROT signals are missing
cocotb==1.6.2
cocotbext-axi==0.1.16
Questa Sim-64 Version 10.7f
Hello,
I am instantiate AxiLiteMaster like this:
axi_drv = AxiLiteMaster(AxiLiteBus.from_entity(dut.axi4_lite_if_inst), dut.i_clk, dut.i_rst_n)
There is an SystemVerilog's interface instance in Top module that contains all of the signals. All signals except aforementioned ones are found and basic READ/WRITE operations are working. What can causing this problem?
Also I noticed that if I do not specify cocotbext-axi's version for simulation it downloads 0.1.18 version and WSTRB signal go missing too.
Logs:
0.00ns INFO AXI lite master signals:
0.00ns INFO araddr width: 32 bits
0.00ns INFO arprot: not present
0.00ns INFO arready width: 1 bits
0.00ns INFO arvalid width: 1 bits
0.00ns INFO rdata width: 32 bits
0.00ns INFO rready width: 1 bits
0.00ns INFO rresp: not present
0.00ns INFO rvalid width: 1 bits
0.00ns INFO AXI lite master signals:
0.00ns INFO awaddr width: 32 bits
0.00ns INFO awprot: not present
0.00ns INFO awready width: 1 bits
0.00ns INFO awvalid width: 1 bits
0.00ns INFO wdata width: 32 bits
0.00ns INFO wready width: 1 bits
0.00ns INFO wstrb width: 4 bits
0.00ns INFO wvalid width: 1 bits
0.00ns INFO bready width: 1 bits
0.00ns INFO bresp: not present
0.00ns INFO bvalid width: 1 bits
Is it possible to force const high TREADY from the testbench?
In some implementations it is possible to use tready as optional port. While the module has a physical tready port for source and sink interfaces it is not required to use these ports. The port would be tied to const "1" on the master side of the module if not needed. Xilinx even has a HAS_TREADY flag as part of some of their IPs that is auto-propagation to connected IPs - only used in the in the block design implementation flow.
I was experimenting and trying to find a way that would allow for automatic test coverage for both cases. It would be testing with toggling TREADY and back-pressure etc. in one case and with static TREADY forced by the testbench in the second case.
You could argue that an active high on TREADY should always work for the module and that it doesn't need to be tested separately. I found that I often end up with a design variation as part of the module that is more resource efficient for this case (bypassed additional registers, fifos, skid-buffers, etc.). Testing it in both configurations gives peace of mind since the design is not exactly the same anymore.
I didn't find a way that would keep TREADY high-all the time and I was wondering if I missed something or if you have an idea how to facilitate the static high TREADY.
using source() when dut has multiple inputs
I have a complex multiplier with two axis inputs. I could not figure out how to use the source in this case. My workaround is to send data manually. Is there a better solution using the source?
My code looks like this
@cocotb.test()
async def multiple_multiplications_(dut):
tb = TB(dut)
await tb.cycle_reset()
tb.sink.queue = deque() # remove remaining items from last test
test_frames = []
for i in range(20):
a_bytes = get_bytes(int(tb.input_width_a/8),random_data())
b_bytes = get_bytes(int(tb.input_width_b/8),random_data())
dut.s_axis_a_tdata <= int.from_bytes(a_bytes, byteorder='big', signed=False)
dut.s_axis_b_tdata <= int.from_bytes(b_bytes, byteorder='big', signed=False)
test_frame = AxiStreamFrame([a_bytes,b_bytes])
test_frames.append(test_frame)
await RisingEdge(dut.clk)
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
receivedData = (rx_frame.tdata[0]).to_bytes(byteorder='big', length=int(tb.output_width/8), signed=False)
received_r = receivedData[int(len(receivedData)/2):len(receivedData)]
received_i = receivedData[0:int(len(receivedData)/2)]
model = Model(tb.input_width_a,tb.input_width_b,tb.output_width)
calculatedData = model.calculate(test_frame.tdata[0],test_frame.tdata[1])
calculated_i = calculatedData[0:int(tb.output_width/8/2)]
calculated_r = calculatedData[int(tb.output_width/8/2):int(tb.output_width/8)]
assert received_r == calculated_r, ("real part should have been %i but was %i " %
(int.from_bytes(calculated_r,byteorder='big',signed=True),int.from_bytes(received_r,byteorder='big',signed=True)))
assert received_i == calculated_i, ("imaginary part should have been %i but was %i " %
(int.from_bytes(calculated_i,byteorder='big',signed=True),int.from_bytes(received_i,byteorder='big',signed=True)))
assert calculatedData == receivedData, ("Error, expected %s got %s" % (calculatedData.hex(), receivedData.hex()))
await RisingEdge(dut.clk)
Edit: how can I make the code show up correctly in this post?
Missing signal results in AssertionError During handling of the above exception, another exception occurred:
While instantiating and AxiSlave or AxiMaster object if the dut does not contain a required signal (eg one of id's) or the signal width is different, then instead of printing the assertion statement I get something like
Traceback (most recent call last):
File "/p/venv/lib64/python3.6/site-packages/cocotb/scheduler.py", line 633, in _resume_coro_upon
trigger.prime(self._react)
File "/p/venv/lib64/python3.6/site-packages/cocotb/triggers.py", line 685, in prime
callback(self)
File "/p/venv/lib64/python3.6/site-packages/cocotb/scheduler.py", line 384, in _react
self._event_loop(trigger)
File "/p/venv/lib64/python3.6/site-packages/cocotb/scheduler.py", line 487, in _event_loop
self._schedule(coro, trigger=trigger)
File "/p/venv/lib64/python3.6/site-packages/cocotb/scheduler.py", line 957, in _schedule
self._unschedule(coroutine)
File "/p/venv/lib64/python3.6/site-packages/cocotb/scheduler.py", line 571, in _unschedule
self._cleanup()
File "/p/venv/lib64/python3.6/site-packages/cocotb/scheduler.py", line 1094, in _cleanup
assert not self._pending_coros
AssertionError
During handling of the above exception, another exception occurred:
Traceback (most recent call last):
File "/p/venv/lib64/python3.6/site-packages/cocotb/__init__.py", line 233, in _initialise_testbench
_initialise_testbench_(argv_)
File "/p/venv/lib64/python3.6/site-packages/cocotb/__init__.py", line 322, in _initialise_testbench_
regression_manager._execute()
File "/p/venv/lib64/python3.6/site-packages/cocotb/regression.py", line 554, in _execute
return self._start_test()
File "/p/venv/lib64/python3.6/site-packages/cocotb/regression.py", line 576, in _start_test
cocotb.scheduler._add_test(self._test_task)
File "/p/venv/lib64/python3.6/site-packages/cocotb/scheduler.py", line 844, in _add_test
NullTrigger(name=f"Start {test_coro!s}", outcome=outcomes.Value(None)),
File "/p/venv/lib64/python3.6/site-packages/cocotb/scheduler.py", line 636, in _resume_coro_upon
self._trigger2coros.pop(trigger)
KeyError: <NullTrigger for Start <Test test_digital> at 0x7f34beb70208>
0.00ns ERROR cocotb.scheduler Failing test at simulator request before test run completion: Simulator shut do
wn prematurely
Correct timeout approach for AxiMaster class
Hey @alexforencich,
what's the correct approach to using a timeout timer in an AxiMaster for writes/reads? I tried the following seq. but it's doesn't work, it complains about wait method not being a trigger type, so it can't be used in conjunction with with_timeout...
taxi
axi_if = AxiMaster(AxiBus.from_prefix(dut, "axi"), dut.clk, dut.arst)
axi_if.init_write(address, data)
await with_timeout(axi_if.wait(), *timeout_val)If it's not clear, I want to have the timer to ensure the slave doesn't hang in the transaction request.
Thanks!
Enhancement of the logging entries
I have two suggestions that would improve the logging functionality.
1. First lets take the AXIS test script as example. It has a Source, Sink and Monitor. I think it would help during debugging if it were possible to tell which log entry is the monitor. In the example case you see:
- "RX frame: AxiStreamFrame(tdata=bytearray(b' ... "
- "RX frame: AxiStreamFrame(tdata=bytearray(b' ... "
It makes sense the way it is but it may be confusing at first and you have to think about it for a second.
Maybe a solution could be to change the log entry to:
"MON frame: AxiStreamFrame(tdata=bytearray(b' ... "
2. If you test a Verilog module with multiple AXIS sources and sinks it will get really difficult because all log entries look very similar and it is very hard to tell them apart.
I suggest to display the bus name as part of the log entry for source, sink, and for the monitor description. I think that would improve the log output and give a better overview.
Just realized that I only looked at the INFO level so far. So please disregard if this exists already.
AxiBus.from_prefix does not recognize capital suffix
Hi,
I have a source file with capital suffix such as _ARADDR,it seems AxiBus.from_prefix() can not recognize it.
manually set tlast=1 when sending the last sample
I am using AxiStreamSource to write to the DUT, I am sending 8 samples of 12 bits each and I want to set tlast high only after all the samples are written, how can I do it?
Latest version
According to the front page, the latest version is v0.1.16. But there is a tag v0.1.18 and also a commit with message Release v0.1.18
What is the reason, why v0.1.18 has not been released completely?
address may exeed signal width
cocotbext-axi/cocotbext/axi/axil_master.py
Line 503 in e21b9ff
with this approach if start address is big enough final address may exeed width of signal in the interfaces, which leads to a simulation failure
Also, can you please give a comment on why "cycles" is necessary? For example, i can see simulations, where burst == FIXED, and then this request is divided into a number of cycles, all with different addresses
AxiLiteSlave: object has no attribute 'aw'
I found the issue trying to verify an AXI Lite master that I am developing. Maybe I am doing something wrong (I didn't find an example using it). Anyway, the easy way to see the problem in action:
- Change the content of
tests/axil/test_axil.pywith:
import cocotb
from cocotbext.axi import AxiLiteBus, AxiLiteMaster, AxiLiteSlave
@cocotb.test()
async def test_master(dut):
axil_mst = AxiLiteMaster(AxiLiteBus.from_prefix(dut, 'axil'), dut.clk, dut.rst)
@cocotb.test()
async def test_slave(dut):
axil_slv = AxiLiteSlave(AxiLiteBus.from_prefix(dut, 'axil'), dut.clk, dut.rst)
- Run
make - The result is:
1.00ns INFO test_master passed
1.00ns INFO running test_slave (2/2)
2.00ns INFO test_slave failed
Traceback (most recent call last):
File "/home/rodrigo/repos/0thers-axi/cocotbext-axi/tests/axil/test_axil.py", line 10, in test_slave
axil_slv = AxiLiteSlave(AxiLiteBus.from_prefix(dut, 'axil'), dut.clk, dut.rst)
File "/usr/local/lib/python3.8/dist-packages/cocotbext/axi/axil_slave.py", line 254, in __init__
self.write_if = AxiLiteSlaveWrite(target, bus.write, clock, reset, reset_active_level)
File "/usr/local/lib/python3.8/dist-packages/cocotbext/axi/axil_slave.py", line 41, in __init__
self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}")
AttributeError: 'NoneType' object has no attribute 'aw'
2.00ns INFO **************************************************************************************
** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) **
**************************************************************************************
** test_axil.test_master PASS 1.00 0.00 293.23 **
** test_axil.test_slave FAIL 1.00 0.00 5949.37 **
**************************************************************************************
** TESTS=2 PASS=1 FAIL=1 SKIP=0 2.00 0.04 51.31 **
**************************************************************************************
How to connect callbacks to AXI monitor?
Hello,
I need to connect a few callbacks to AXI-Stream monitor, but as AXI-S's monitor does not inherited from cocotb's "BusMonitor" class, there is no ".add_callback()" method. Is there any method with similar functionality?
Simulation gets stuck with SIM=verilator 4.106
Thanks a lot for this great project! @alexforencich @rodrigomelo9
I am trying to run the axi-verilog designs using verilator, however, this library does not seem to be compatible with verilator. I use version 4.106 which should be compatible with cocotb (all their base examples work).
However, it seems as if the simulation tests are stuck here: https://github.com/alexforencich/cocotbext-axi/blob/master/cocotbext/axi/axi_master.py#L413
Commands for reproduction:
python3 -m pip install cocotbext-axi==0.1.18
git clone https://github.com/alexforencich/cocotbext-axi.git
cd cocotbext-axi/tests/axi/
git checkout v0.1.18
SIM=verilator make
running make without SIM=verilator works
The log for the axi test is:
make -f Makefile results.xml
make[1]: Entering directory '/home/andreas/Desktop/cocotbext-axi/tests/axi'
MODULE=test_axi TESTCASE= TOPLEVEL=test_axi TOPLEVEL_LANG=verilog \
sim_build/Vtop
-.--ns INFO cocotb.gpi ..mbed/gpi_embed.cpp:76 in set_program_name_in_venv Did not detect Python virtual environment. Using system-wide Python interpreter
-.--ns INFO cocotb.gpi ../gpi/GpiCommon.cpp:99 in gpi_print_registered_impl VPI registered
0.00ns INFO Running on Verilator version 4.106 2020-12-02
0.00ns INFO Running tests with cocotb v1.6.1 from /home/andreas/.local/lib/python3.8/site-packages/cocotb
0.00ns INFO Seeding Python random module with 1642601669
0.00ns INFO Found test test_axi.run_test_write_001
0.00ns INFO Found test test_axi.run_test_write_002
0.00ns INFO Found test test_axi.run_test_write_003
0.00ns INFO Found test test_axi.run_test_write_004
0.00ns INFO Found test test_axi.run_test_write_005
0.00ns INFO Found test test_axi.run_test_write_006
0.00ns INFO Found test test_axi.run_test_write_007
0.00ns INFO Found test test_axi.run_test_write_008
0.00ns INFO Found test test_axi.run_test_write_009
0.00ns INFO Found test test_axi.run_test_write_010
0.00ns INFO Found test test_axi.run_test_write_011
0.00ns INFO Found test test_axi.run_test_write_012
0.00ns INFO Found test test_axi.run_test_read_001
0.00ns INFO Found test test_axi.run_test_read_002
0.00ns INFO Found test test_axi.run_test_read_003
0.00ns INFO Found test test_axi.run_test_read_004
0.00ns INFO Found test test_axi.run_test_read_005
0.00ns INFO Found test test_axi.run_test_read_006
0.00ns INFO Found test test_axi.run_test_read_007
0.00ns INFO Found test test_axi.run_test_read_008
0.00ns INFO Found test test_axi.run_test_read_009
0.00ns INFO Found test test_axi.run_test_read_010
0.00ns INFO Found test test_axi.run_test_read_011
0.00ns INFO Found test test_axi.run_test_read_012
0.00ns INFO Found test test_axi.run_test_write_words_001
0.00ns INFO Found test test_axi.run_test_read_words_001
0.00ns INFO Found test test_axi.run_stress_test_001
0.00ns INFO running run_test_write_001 (1/27)
0.00ns INFO AXI master (write)
0.00ns INFO cocotbext-axi version 0.1.18
0.00ns INFO Copyright (c) 2020 Alex Forencich
0.00ns INFO https://github.com/alexforencich/cocotbext-axi
0.00ns INFO Reset de-asserted
0.00ns INFO Reset de-asserted
0.00ns INFO Reset de-asserted
0.00ns INFO AXI master configuration:
0.00ns INFO Address width: 32 bits
0.00ns INFO ID width: 8 bits
0.00ns INFO Byte size: 8 bits
0.00ns INFO Data width: 32 bits (4 bytes)
0.00ns INFO Max burst size: 2 (4 bytes)
0.00ns INFO Max burst length: 256 cycles (1024 bytes)
0.00ns INFO AXI master signals:
0.00ns INFO awaddr width: 32 bits
0.00ns INFO awburst width: 2 bits
0.00ns INFO awcache width: 4 bits
0.00ns INFO awid width: 8 bits
0.00ns INFO awlen width: 8 bits
0.00ns INFO awlock width: 1 bits
0.00ns INFO awprot width: 3 bits
0.00ns INFO awqos width: 4 bits
0.00ns INFO awready width: 1 bits
0.00ns INFO awregion width: 4 bits
0.00ns INFO awsize width: 3 bits
0.00ns INFO awuser width: 1 bits
0.00ns INFO awvalid width: 1 bits
0.00ns INFO wdata width: 32 bits
0.00ns INFO wlast width: 1 bits
0.00ns INFO wready width: 1 bits
0.00ns INFO wstrb width: 4 bits
0.00ns INFO wuser width: 1 bits
0.00ns INFO wvalid width: 1 bits
0.00ns INFO bid width: 8 bits
0.00ns INFO bready width: 1 bits
0.00ns INFO bresp width: 2 bits
0.00ns INFO buser width: 1 bits
0.00ns INFO bvalid width: 1 bits
0.00ns INFO Reset de-asserted
0.00ns INFO AXI master (read)
0.00ns INFO cocotbext-axi version 0.1.18
0.00ns INFO Copyright (c) 2020 Alex Forencich
0.00ns INFO https://github.com/alexforencich/cocotbext-axi
0.00ns INFO Reset de-asserted
0.00ns INFO Reset de-asserted
0.00ns INFO AXI master configuration:
0.00ns INFO Address width: 32 bits
0.00ns INFO ID width: 8 bits
0.00ns INFO Byte size: 8 bits
0.00ns INFO Data width: 32 bits (4 bytes)
0.00ns INFO Max burst size: 2 (4 bytes)
0.00ns INFO Max burst length: 256 cycles (1024 bytes)
0.00ns INFO AXI master signals:
0.00ns INFO araddr width: 32 bits
0.00ns INFO arburst width: 2 bits
0.00ns INFO arcache width: 4 bits
0.00ns INFO arid width: 8 bits
0.00ns INFO arlen width: 8 bits
0.00ns INFO arlock width: 1 bits
0.00ns INFO arprot width: 3 bits
0.00ns INFO arqos width: 4 bits
0.00ns INFO arready width: 1 bits
0.00ns INFO arregion width: 4 bits
0.00ns INFO arsize width: 3 bits
0.00ns INFO aruser width: 1 bits
0.00ns INFO arvalid width: 1 bits
0.00ns INFO rdata width: 32 bits
0.00ns INFO rid width: 8 bits
0.00ns INFO rlast width: 1 bits
0.00ns INFO rready width: 1 bits
0.00ns INFO rresp width: 2 bits
0.00ns INFO ruser width: 1 bits
0.00ns INFO rvalid width: 1 bits
0.00ns INFO Reset de-asserted
0.00ns INFO AXI slave model (write)
0.00ns INFO cocotbext-axi version 0.1.18
0.00ns INFO Copyright (c) 2021 Alex Forencich
0.00ns INFO https://github.com/alexforencich/cocotbext-axi
0.00ns INFO Reset de-asserted
0.00ns INFO Reset de-asserted
0.00ns INFO Reset de-asserted
0.00ns INFO AXI slave model configuration:
0.00ns INFO Address width: 32 bits
0.00ns INFO ID width: 8 bits
0.00ns INFO Byte size: 8 bits
0.00ns INFO Data width: 32 bits (4 bytes)
0.00ns INFO AXI slave model signals:
0.00ns INFO awaddr width: 32 bits
0.00ns INFO awburst width: 2 bits
0.00ns INFO awcache width: 4 bits
0.00ns INFO awid width: 8 bits
0.00ns INFO awlen width: 8 bits
0.00ns INFO awlock width: 1 bits
0.00ns INFO awprot width: 3 bits
0.00ns INFO awqos width: 4 bits
0.00ns INFO awready width: 1 bits
0.00ns INFO awregion width: 4 bits
0.00ns INFO awsize width: 3 bits
0.00ns INFO awuser width: 1 bits
0.00ns INFO awvalid width: 1 bits
0.00ns INFO wdata width: 32 bits
0.00ns INFO wlast width: 1 bits
0.00ns INFO wready width: 1 bits
0.00ns INFO wstrb width: 4 bits
0.00ns INFO wuser width: 1 bits
0.00ns INFO wvalid width: 1 bits
0.00ns INFO bid width: 8 bits
0.00ns INFO bready width: 1 bits
0.00ns INFO bresp width: 2 bits
0.00ns INFO buser width: 1 bits
0.00ns INFO bvalid width: 1 bits
0.00ns INFO Reset de-asserted
0.00ns INFO AXI slave model (read)
0.00ns INFO cocotbext-axi version 0.1.18
0.00ns INFO Copyright (c) 2021 Alex Forencich
0.00ns INFO https://github.com/alexforencich/cocotbext-axi
0.00ns INFO Reset de-asserted
0.00ns INFO Reset de-asserted
0.00ns INFO AXI slave model configuration:
0.00ns INFO Address width: 32 bits
0.00ns INFO ID width: 8 bits
0.00ns INFO Byte size: 8 bits
0.00ns INFO Data width: 32 bits (4 bytes)
0.00ns INFO AXI slave model signals:
0.00ns INFO araddr width: 32 bits
0.00ns INFO arburst width: 2 bits
0.00ns INFO arcache width: 4 bits
0.00ns INFO arid width: 8 bits
0.00ns INFO arlen width: 8 bits
0.00ns INFO arlock width: 1 bits
0.00ns INFO arprot width: 3 bits
0.00ns INFO arqos width: 4 bits
0.00ns INFO arready width: 1 bits
0.00ns INFO arregion width: 4 bits
0.00ns INFO arsize width: 3 bits
0.00ns INFO aruser width: 1 bits
0.00ns INFO arvalid width: 1 bits
0.00ns INFO rdata width: 32 bits
0.00ns INFO rid width: 8 bits
0.00ns INFO rlast width: 1 bits
0.00ns INFO rready width: 1 bits
0.00ns INFO rresp width: 2 bits
0.00ns INFO ruser width: 1 bits
0.00ns INFO rvalid width: 1 bits
0.00ns INFO Reset de-asserted
2.00ns INFO Reset asserted
2.00ns INFO Reset asserted
2.00ns INFO Reset asserted
2.00ns INFO Reset asserted
2.00ns INFO Reset asserted
2.00ns INFO Reset asserted
2.00ns INFO Reset asserted
2.00ns INFO Reset asserted
2.00ns INFO Reset asserted
2.00ns INFO Reset asserted
2.00ns INFO Reset asserted
2.00ns INFO Reset asserted
2.00ns INFO Reset asserted
2.00ns INFO Reset asserted
2.00ns INFO Reset de-asserted
2.00ns INFO Reset de-asserted
2.00ns INFO Reset de-asserted
2.00ns INFO Reset de-asserted
2.00ns INFO Reset de-asserted
2.00ns INFO Reset de-asserted
2.00ns INFO Reset de-asserted
2.00ns INFO Reset de-asserted
2.00ns INFO Reset de-asserted
2.00ns INFO Reset de-asserted
2.00ns INFO Reset de-asserted
2.00ns INFO Reset de-asserted
2.00ns INFO Reset de-asserted
2.00ns INFO Reset de-asserted
10.00ns INFO length 1, offset 0
10.00ns INFO Write start addr: 0x00001000 awid: 0x0 prot: AxiProt.NONSECURE data: 00
10.00ns INFO Write burst start awid: 0x0 awaddr: 0x00001000 awlen: 0 awsize: 2 awprot: AxiProt.NONSECURE
[Question] _init_x = True
In class AxiStreamSource (axis.py line 402) the variable _init_x is set to True. This forces all signals to X until they are used.
What is the idea behind this?
From a source driver I would expect to output a valid state all the time.
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