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adc_block_ram_spi_top

Xilinx Artix-7 FPGA design using block ram, XADC and a SPI slave (SCARF). The block ram is dual port and can be written by either SPI or XADC samples, and only read by SPI.

atmega328-motor-board

Placa controladora para motores controlada por un microcontrolador ATMEGA328

attitude-estimation

MatLAB and Python implementations for 6-DOF IMU attitude estimation using Kalman Filters, Complementary Filters, etc.

av-swe-guide

An autonomous vehicle guide for computer science students and software engineers

awesome

A curated list of awesome resources for HDL design and verification

awesome-electronics

A curated list of awesome resources for electronic engineers and hobbyists

awesome-opensource-hardware

List of awesome open source hardware tools, generators, and reusable designs

awesome-robotic-tooling

Tooling for professional robotic development in C++ and Python with a touch of ROS, autonomous driving and aerospace: https://freerobotics.tools/

awesome-robotics

A list of awesome Robotics resources

awesome-rtc

:satellite: A curated list of awesome Real Time Communications resources

awesome_photonics

😎 curated list of open source photonics projects

axi-protocol-interconnect-design-and-implementation-

axi2spi-bridge

Homework for Rendszerarchitekturak with Feher Béla & Wacha Gabor :)

axi4_master_interconnect_slave

A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple masters arbitration. Simulation waveforms are also included.

axi4bus

一套AXI4 interconnect 组件，通过简单连接可以搭建需要的AXI interconnect。

bluepill-serial-monster

USB to 3 Port Serial (UART) adapter firmware for STM32 Blue Pill.

caravel_sirius

caravel_sirius_chip

https://caravel-user-project.readthedocs.io

cmod_a7_spi_sram

SPI slave to External SRAM interface for Cmod A7

cmsis

Cortex Microcontroller Software Interface Standard

computer-science

:mortar_board: Path to a free self-taught education in Computer Science!

core-v-docs

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

cores-swerv

SweRV EH1 core

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

data-structures-in-c

This repo contains example codes for data structures in C language.

dual-core-risc-v-processor

A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.

esnet-fpga-library

ESnet general-purpose FPGA design library.

fabacademy-tutorials

[OUTDATED] A living collection of tutorials to support Fab Academy http://docs.academany.org/FabAcademy-Tutorials/_book/