Comments (4)
I'm in the process of completely rebuilding the reset implementation. The new implementation at its core supports both polarities, but I'm not sure the best way to expose that at the top-level. Might just need to add another parameter to the constructor, I will ask about this on the cocotb gitter to see if anyone has any better ideas.
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Also, I should mention that with the current setup, resets really don't work correctly, so you're better off leaving it disconnected until I get it fixed up properly.
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I have the same issue, I want to implement a core that is compatible to Xilinx AXIS cores. They use active low reset.
The sink never receives data if I do
self.sink = AxiStreamSink(dut, "m_axis", dut.clk, dut.nrst)
doing
self.sink = AxiStreamSink(dut, "m_axis", dut.clk, not dut.nrst)
does not work
for now I disconnected the reset, so the simulation does not freeze.
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The latest release of cocotbext-axi adds the reset_active_level
parameter to the constructors. Set this to False
for an active-low reset.
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Related Issues (20)
- 0.1.20 makes my tests fail HOT 43
- axi address width causing overflow HOT 5
- address may exeed signal width HOT 2
- Axi Streaming is missing support for tstrb
- Is the repo unmaintained / closed to new features? HOT 2
- AxiStreamSink cannot handle tdata X-bytes for bytes to ignore (tkeep=0) HOT 1
- Missing signal results in AssertionError During handling of the above exception, another exception occurred: HOT 5
- Axis DUT signal naming HOT 1
- manually set tlast=1 when sending the last sample HOT 4
- Something is broken between 0.1.20 and 0.1.22
- AxiStreamSink not reading signed_int from dut HOT 5
- Conditional logging
- No support for suffixed AXI bus signal names
- AxiStreamSource shows unexpected behaviour with TUSER and multiple byte_lanes HOT 4
- Setting optional arguments arid,awid in AxiMaster don't seem to work
- Axi stream receiving 8b chunks when sending 32b data HOT 3
- Assigning value to individual signals of AXI Read Address Channel HOT 9
- Issue accessing AXI4Lite bus signals wrapped in a VHDL record HOT 2
- AxiStreamMonitor: Monitor AXIS in a hierarchy deeper than top dut HOT 1
- Writing to / Reading of AxiRam from the hardware DUT hang when adding when loops to the test bench
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