hxfabc2012 Goto Github PK

followers: 1.0 following: 2.0 repos: 90.0 gists: 0.0

Type: User

hxfabc2012's Projects

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

async_fifo_verification

Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.

axi-uvm

yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/

buildroot

forked from https://git.busybox.net/buildroot/

cnn_hw_accelerator

Hardware accelerator of a CNN on Xilinx ZYNQ running on PetaLinux

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

cocotbext-pcie

PCI express simulation framework for Cocotb

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

ddr5_phy

DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

fpga_dpu

This project is to implement YOLO v3 on Xilinx FPGA with DPU

Free TPU for FPGA with Lenet, MobileNet, Squeezenet, Resnet, Inception V3, YOLO V3, and ICNet. Deep learning acceleration using Xilinx zynq (Zedboard or ZC702 ) or kintex-7 to solve image classification, detection, and segmentation problem.

fusionaccel

RTL-level Convolutional Network Accelerator Implementation on Xilinx Spartan 6. Evaluation for scalability.

hdl

HDL libraries and projects

hello

study how to use git

hw

RTL, Cmodel, and testbench for NVDLA

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

libyunsdr

Library for YunSDR device

linux

Linux kernel variant from Analog Devices; see README.md for details

lowrisc-chip

The root repo for lowRISC project and FPGA demos.

mempool

A 256-RISC-V-core system with low-latency access into shared L1 memory.

mipsverification_uvm

Verification of a MIPS Multi-Cycle Microprocessor using UVM

hxfabc2012 Goto Github PK

hxfabc2012's Projects

Recommend Projects

Recommend Topics

Recommend Org