Comments (1)
kirill-bessonov
commented on May 29, 2024
Solution has been founded.
This string:
self.axi_drv = AxiLiteMaster(AxiLiteBus.from_prefix(self.dut, "AXI4_LITE_"), self.dut.i_clk, self.dut.i_rst_n)
will search for "_xxx" signals i.e. with underscore.
This string:
self.axi_drv = AxiLiteMaster(AxiLiteBus.from_prefix(self.dut, "AXI4_LITE"), self.dut.i_clk, self.dut.i_rst_n)
will search for "xxx" signals i.e. without underscore, that will correspond to correct names as ["data", "valid", "ready"].
from cocotbext-axi.
Related Issues (20)
- Manually set a bus signal as optional even if present HOT 5
- 0.1.20 makes my tests fail HOT 43
- axi address width causing overflow HOT 5
- address may exeed signal width HOT 2
- Axi Streaming is missing support for tstrb
- Is the repo unmaintained / closed to new features? HOT 2
- AxiStreamSink cannot handle tdata X-bytes for bytes to ignore (tkeep=0) HOT 1
- Missing signal results in AssertionError During handling of the above exception, another exception occurred: HOT 5
- Axis DUT signal naming HOT 1
- manually set tlast=1 when sending the last sample HOT 4
- Something is broken between 0.1.20 and 0.1.22
- AxiStreamSink not reading signed_int from dut HOT 5
- Conditional logging
- No support for suffixed AXI bus signal names
- AxiStreamSource shows unexpected behaviour with TUSER and multiple byte_lanes HOT 4
- Setting optional arguments arid,awid in AxiMaster don't seem to work
- Axi stream receiving 8b chunks when sending 32b data HOT 3
- Assigning value to individual signals of AXI Read Address Channel HOT 9
- Issue accessing AXI4Lite bus signals wrapped in a VHDL record HOT 2
- AxiStreamMonitor: Monitor AXIS in a hierarchy deeper than top dut HOT 1
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from cocotbext-axi.