Comments (5)
Define what you mean by "byte swapping".
from cocotbext-axi.
With byte swapping I mean controlling how the data bytes are presented left to right on the tdata/tkeep signals. Would be nice if both little endian and big endian was supported.
from cocotbext-axi.
The AXI stream specification is very specific about byte ordering:
I'm already bending the spec by supporting byte sizes of other than 8 bits (which I think is reasonable). However, if your IP expects the first byte to start on a byte lane other than [n:0], then it's not AXI stream compliant, and the most reasonable way forward is to write an HDL shim to convert your IP to AXI stream.
from cocotbext-axi.
OK, understand if you prefer not to introduce non-standard features.
I’ll use a shim to work around the issue.
Thanks
from cocotbext-axi.
Let me put it to you this way: I'm not necessarily opposed to it, but I'll have to be convinced it would be a useful feature, and to do that you'll have to overcome 1. the fact that the AXI stream spec is very explicit about byte ordering, and 2. my opinion that big endian makes no sense whatsoever and therefore should never be used, except inside of packet headers that require network byte order. Avalon is a slightly different story as it seems like it supports both orderings, just to make things more confusing.
from cocotbext-axi.
Related Issues (20)
- axi address width causing overflow HOT 5
- address may exeed signal width HOT 2
- Axi Streaming is missing support for tstrb
- Is the repo unmaintained / closed to new features? HOT 2
- AxiStreamSink cannot handle tdata X-bytes for bytes to ignore (tkeep=0) HOT 1
- Missing signal results in AssertionError During handling of the above exception, another exception occurred: HOT 5
- Axis DUT signal naming HOT 1
- manually set tlast=1 when sending the last sample HOT 4
- Something is broken between 0.1.20 and 0.1.22
- AxiStreamSink not reading signed_int from dut HOT 5
- Conditional logging
- No support for suffixed AXI bus signal names
- AxiStreamSource shows unexpected behaviour with TUSER and multiple byte_lanes HOT 4
- Setting optional arguments arid,awid in AxiMaster don't seem to work
- Axi stream receiving 8b chunks when sending 32b data HOT 3
- Assigning value to individual signals of AXI Read Address Channel HOT 9
- Issue accessing AXI4Lite bus signals wrapped in a VHDL record HOT 2
- AxiStreamMonitor: Monitor AXIS in a hierarchy deeper than top dut HOT 1
- Writing to / Reading of AxiRam from the hardware DUT hang when adding when loops to the test bench
- cocotb-bus.bus implements the bus_separator to which you removed access to the axi-lite
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