Comments (8)
Ah yep, there were a couple of bugs there that I have sorted out, will push a fix soon. There aren't really any examples of the AXI/AXI lite slave modules as they are a bit special purpose, normally you'll probably want to use the AXI/AXI lite RAM, which is an extension of the AXI/AXI lite slave.
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Got it, I'm going to try with the AXI/AXIL RAM and let you know.
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I successfully used AxiLiteRAM with my AXI4 Lite master (and I fixed some issues as consequence). Great idea to easily check the basic functionality of a master ;-)
I have a question: whenever I set AxPROT with a value different to 1, 2 or 4, I receive a ValueError:
13.00ns INFO test_basic failed
ValueError: 011 is not a valid AxiProt
As far I know, any combination is valid, right? I never worry about AxPROT before, but I used it as 000 in the past without problems (Xilinx).
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Hmm, that's very odd. Is there a line number associated with that exception? AxiProt
should be a flag field, and as such all combinations of bits should be valid.
In [1]: from cocotbext.axi import AxiProt
In [2]: AxiProt(0b011)
Out[2]: <AxiProt.NONSECURE|PRIVILEGED: 3>
And the default that you should normally be using is 0b010
, as this sets the "nonsecure" bit. Although it won't make a difference unless you're using something like ARM TrustZone, in which case using 0b000
could end up allowing a device to bypass the TrustZone protections. The idea is that the interconnect components can have "secure" devices that are only accessible by operations with the nonsecure bit clear, and the CPU will issue operations with this bit clear only when operating in certain secure execution modes, and with the bit set in non-secure execution modes.
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I am using AxiLiteRAM:
axil_ram = AxiLiteRam(AxiLiteBus.from_entity(dut), dut.aclk)
And here is the exception:
32.00ns INFO The core was reset
36.00ns ERROR Exception raised by this forked coroutine
37.00ns INFO test_burst failed
ValueError: 000 is not a valid AxiProt
During handling of the above exception, another exception occurred:
Traceback (most recent call last):
File "/usr/local/lib/python3.8/dist-packages/cocotbext/axi/axil_slave.py", line 110, in _process_write
prot = AxiProt(getattr(aw, 'awprot', AxiProt.NONSECURE))
File "/usr/lib/python3.8/enum.py", line 339, in __call__
return cls.__new__(cls, value)
File "/usr/lib/python3.8/enum.py", line 670, in __new__
raise exc
File "/usr/lib/python3.8/enum.py", line 653, in __new__
result = cls._missing_(value)
File "/usr/lib/python3.8/enum.py", line 895, in _missing_
raise ValueError("%r is not a valid %s" % (value, cls.__name__))
ValueError: 000 is not a valid AxiProt
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Hmm, looks like I need to explicitly convert that to an integer before converting to AxiProt
.
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Try again with the current git version and let me know if you're still seeing the same issue.
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Yes, it works with the current version at master :-D
Based on one of the last logs (Fix AxiLiteSlave wrapper), I re-check axil_slv = AxiLiteSlave(AxiLiteBus.from_entity(dut), dut.aclk)
and it also works, so this issue can be closed.
Thanks Alex, I am very happy using cocotbext-axi in the development of AXI masters at my job ;-) I think that is a very valuable project.
Regards,
Rodrigo
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Related Issues (20)
- 0.1.20 makes my tests fail HOT 43
- axi address width causing overflow HOT 5
- address may exeed signal width HOT 2
- Axi Streaming is missing support for tstrb
- Is the repo unmaintained / closed to new features? HOT 2
- AxiStreamSink cannot handle tdata X-bytes for bytes to ignore (tkeep=0) HOT 1
- Missing signal results in AssertionError During handling of the above exception, another exception occurred: HOT 5
- Axis DUT signal naming HOT 1
- manually set tlast=1 when sending the last sample HOT 4
- Something is broken between 0.1.20 and 0.1.22
- AxiStreamSink not reading signed_int from dut HOT 5
- Conditional logging
- No support for suffixed AXI bus signal names
- AxiStreamSource shows unexpected behaviour with TUSER and multiple byte_lanes HOT 4
- Setting optional arguments arid,awid in AxiMaster don't seem to work
- Axi stream receiving 8b chunks when sending 32b data HOT 3
- Assigning value to individual signals of AXI Read Address Channel HOT 9
- Issue accessing AXI4Lite bus signals wrapped in a VHDL record HOT 2
- AxiStreamMonitor: Monitor AXIS in a hierarchy deeper than top dut HOT 1
- Writing to / Reading of AxiRam from the hardware DUT hang when adding when loops to the test bench
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