Comments (4)
I should probably enable discussions on the cocotbext repos. Anyway, that's a rather odd way to split things out. Right now I don't think it's possible to connect that up, but I'm looking in to reworking how the bus object is used to make this sort of thing easier/possible. Worse comes to worse, you'll be able to manually connect all of the signals. In your case, it looks like maybe having some way to combine signals from two objects into one object might make this unnecessary. Something like this, perhaps:
axi_if = [AxiMaster(mosi + miso, dut.clk, dut.rst, ...) for mosi, miso in zip(dut.inst.axi_mosi_if, dut.inst.axi_miso_if]
or perhaps:
axi_if = [AxiMaster(Combine(mosi, miso), dut.clk, dut.rst, ...) for mosi, miso in zip(dut.inst.axi_mosi_if, dut.inst.axi_miso_if]
I'll discuss with the cocotb folks about the feasibility of making something like this work.
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I just added new objects that will hopefully be able to make this sort of thing easier. Right now they are just wrappers around the Bus
object, but I'm planning on doing a more complete rewrite. I'm not sure exactly what it's going to look like at this point, but I'm definitely going to keep this particular use-case in mind, perhaps by supporting matching signals from multiple source entities.
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oh great, thanks for the heads up! Please keep as an example too if possible.... This type of usage is very common in ASIC industry once it helps with bus integration and during the synthesis steps when you need to constrain in/outs
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btw, if you're willing to have something in SV, use Verilator 4.106 once the latest is hanging due to VPI changes
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Related Issues (20)
- Manually set a bus signal as optional even if present HOT 5
- 0.1.20 makes my tests fail HOT 43
- axi address width causing overflow HOT 5
- address may exeed signal width HOT 2
- Axi Streaming is missing support for tstrb
- Is the repo unmaintained / closed to new features? HOT 2
- AxiStreamSink cannot handle tdata X-bytes for bytes to ignore (tkeep=0) HOT 1
- Missing signal results in AssertionError During handling of the above exception, another exception occurred: HOT 5
- Axis DUT signal naming HOT 1
- manually set tlast=1 when sending the last sample HOT 4
- Something is broken between 0.1.20 and 0.1.22
- AxiStreamSink not reading signed_int from dut HOT 5
- Conditional logging
- No support for suffixed AXI bus signal names
- AxiStreamSource shows unexpected behaviour with TUSER and multiple byte_lanes HOT 4
- Setting optional arguments arid,awid in AxiMaster don't seem to work
- Axi stream receiving 8b chunks when sending 32b data HOT 3
- Assigning value to individual signals of AXI Read Address Channel HOT 9
- Issue accessing AXI4Lite bus signals wrapped in a VHDL record HOT 2
- AxiStreamMonitor: Monitor AXIS in a hierarchy deeper than top dut HOT 1
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