vslide is a crucial requirement to efficiently run convolutions. Therefore, it needs to be implemented before adding the conv2d kernel.

xtensor is a C++ library for high-performance ND array computing. Among other things, it implements lazy evaluation, which performs loop fusion and avoids temporaries. So it is well suited to be run on a vector/SIMD CPU such as RISC-V with Vector extension.
xsimd is an abstraction layer around various SIMD architectures (Intel, Arm...), and xtensor supports xsimd to accelerate computations. We would like to support RISC-V Vector extension in xsimd, and ara is one of the only open-source projects that I know of which implements the Vector extension.
Do you think it is ready to be used for that purpose? We will need to evaluate performances, is the RTL model the only cycle-accurate model, or are there higher-level behavioral models?

Could you please make very small configurations possible? This is for a design verification effort and the ideal configuration would be NR_LANES=1, VLEN=128. And while waiting for the changes that would make this small config build properly, could you please state what is the smallest setting that builds correctly today and has been tested?

The store unit commits an off-by-one error when tries to store arrays that are not 128-bit aligned in memory (128-bit is the AXI data width). For now, benchmarks work on 128-bit aligned data to overcome this issue.

Following the official specifications, RISC-V vector arithmetical instructions use vs2 as the first/only operand and vs1 as the second operand. However, the current mapping from vector registers to operand queues is:

• vs1 to OpQueueA
• vs2 to OpQueueB
• vd to OpQueueC

This mapping is not intuitive, as the first/only operand goes to OpQueueB. I propose to change the mapping to:

• vs1 to OpQueueB
• vs2 to OpQueueA
• vd to OpQueueC

I failed to build toolchain-llvm on MacOS.
There are several similar errors, and the first FAILED log is as follows:

I'm not sure if these warning logs previous to the FAILED logs will be helpful for debugging.

I got core dump when dump waveform in Verilator.

Here is my patch.

diff --git a/hardware/Makefile b/hardware/Makefile
index 7a4c666..175fbfa 100644
--- a/hardware/Makefile
+++ b/hardware/Makefile
@@ -176,19 +176,20 @@ $(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell fi
   $(ROOT_DIR)/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/*.cc      \
   $(ROOT_DIR)/tb/verilator/ara_tb.cpp                                           \
   --cc                                                                          \
+  $(if $(DEBUG),--trace-fst -Wno-INSECURE,)                                     \
   --top-module $(veril_top) &&                                                  \
 	cd $(veril_library) && OBJCACHE='' make -j4 -f V$(veril_top).mk
 
 # Simulation
 .PHONY: simv
 simv:
-	$(veril_library)/V$(veril_top) -l ram,$(app_path)/$(app),elf
+	$(veril_library)/V$(veril_top) $(if $(DEBUG),-t,) -l ram,$(app_path)/$(app),elf
 
 .PHONY: riscv_tests_simv
 riscv_tests_simv: $(tests)
 
 $(tests): rv%: $(app_path)/rv%
-	$(veril_library)/V$(veril_top) -l ram,$<,elf &> $(buildpath)/[email protected]
+	$(veril_library)/V$(veril_top) $(if $(DEBUG),-t,) -l ram,$<,elf &> $(buildpath)/[email protected]
 
 # DPIs
 .PHONY: dpi
diff --git a/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/verilated_toplevel.h b/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/verilated_toplevel.h
index 1d7cc7d..e6c8d58 100644
--- a/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/verilated_toplevel.h
+++ b/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/verilated_toplevel.h
@@ -31,10 +31,10 @@
 #define VM_TRACE 0
 #endif
 
-// VM_TRACE_FMT_FST must be set by the user when calling Verilator with
+// VM_TRACE_FST must be set by the user when calling Verilator with
 // --trace-fst. VM_TRACE is set by Verilator itself.
 #if VM_TRACE == 1
-#ifdef VM_TRACE_FMT_FST
+#ifdef VM_TRACE_FST
 #include "verilated_fst_c.h"
 #define VM_TRACE_CLASS_NAME VerilatedFstC
 #else
diff --git a/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/verilator_sim_ctrl.cc b/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/verilator_sim_ctrl.cc
index 0721d7c..fad078f 100644
--- a/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/verilator_sim_ctrl.cc
+++ b/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/verilator_sim_ctrl.cc
@@ -264,7 +264,7 @@ void VerilatorSimCtrl::PrintStatistics() const {
 }
 
 const char *VerilatorSimCtrl::GetTraceFileName() const {
-#ifdef VM_TRACE_FMT_FST
+#ifdef VM_TRACE_FST
   return "sim.fst";
 #else
   return "sim.vcd";
@@ -280,6 +280,8 @@ void VerilatorSimCtrl::Run() {
     top_->trace(tracer_, 99, 0);
   }
 
+  Trace();
+
   // Evaluate all initial blocks, including the DPI setup routines
   top_->eval();
 
@@ -288,7 +290,6 @@ void VerilatorSimCtrl::Run() {
 
   time_begin_ = std::chrono::steady_clock::now();
   UnsetReset();
-  Trace();
 
   unsigned long start_reset_cycle_ = initial_reset_delay_cycles_;
   unsigned long end_reset_cycle_ = start_reset_cycle_ + reset_duration_cycles_;

I did the following patch,

1. Solve the core dump issue
2. Change macro VM_TRACE_FMT_FST to VM_TRACE_FST to support fst waveform dump.
3. Add DEBUG in Makefile to generate the waveform (default fst format)

Users can use the following command to generate trace for Verilator

$ make verilate DEBUG=1

Using following command to run the diag

$ make simv app=benchmarks DEBUG=1

When I run this command:

~/ara/hardware$make apply-patches 

I face this error:

Makefile:62: "Specified QuestaSim version (questa-2020.1) not found in PATH /home/hpc-user/xilinx/Vivado/2016.2/bin:/home/hpc-user/intelFPGA_pro/21.2/modelsim_ase/bin:/usr/bin/sbt:/home/hpc-user/riscv-gnu-toolchain/build/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin"
cd deps/tech_cells_generic && git apply ../../patches/0001-tech-cells-generic-sram.patch
error: patch failed: src/rtl/tc_sram.sv:124
error: src/rtl/tc_sram.sv: patch does not apply
make: *** [Makefile:101: apply-patches] Error 1

I ignored this error, and I ran the next one:

~/ara/hardware$make verilate

Again, I face this error:

Makefile:62: "Specified QuestaSim version (questa-2020.1) not found in PATH /home/hpc-user/xilinx/Vivado/2016.2/bin:/home/hpc-user/intelFPGA_pro/21.2/modelsim_ase/bin:/usr/bin/sbt:/home/hpc-user/riscv-gnu-toolchain/build/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin"
mkdir -p build
rm -rf build/verilator; mkdir -p build/verilator
./bender script verilator -t rtl -t ara_test -t cva6_test -t verilator --define NR_LANES=4 --define VLEN=4096 --define RVV_ARIANE=1 > build/verilator/bender_script_default
bash: ./bender: No such file or directory
make: *** [Makefile:145: build/verilator/Vara_tb_verilator] Error 127
make: *** Waiting for unfinished jobs....
Successfully installed bender 0.21.0 in '/home/hpc-user/ara/hardware'.
bender 0.21.0 available.

The Second Time I run this command, face:

Makefile:62: "Specified QuestaSim version (questa-2020.1) not found in PATH /home/hpc-user/xilinx/Vivado/2016.2/bin:/home/hpc-user/intelFPGA_pro/21.2/modelsim_ase/bin:/usr/bin/sbt:/home/hpc-user/riscv-gnu-toolchain/build/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin"
rm -rf build/verilator; mkdir -p build/verilator
./bender script verilator -t rtl -t ara_test -t cva6_test -t verilator --define NR_LANES=4 --define VLEN=4096 --define RVV_ARIANE=1 > build/verilator/bender_script_default
/home/hpc-user/ara/install/verilator/bin/verilator -f build/verilator/bender_script_default           \
  -GNrLanes=4                                                         \
  -O3                                                                           \
  -Wno-BLKANDNBLK                                                               \
  -Wno-CASEINCOMPLETE                                                           \
  -Wno-CMPCONST                                                                 \
  -Wno-LATCH                                                                    \
  -Wno-LITENDIAN                                                                \
  -Wno-UNOPTFLAT                                                                \
  -Wno-UNPACKED                                                                 \
  -Wno-UNSIGNED                                                                 \
  -Wno-WIDTH                                                                    \
  -Wno-WIDTHCONCAT                                                              \
  --hierarchical                                                                \
  tb/verilator/waiver.vlt                                                       \
  --Mdir build/verilator                                                       \
  -Itb/dpi                                                                      \
  --compiler clang                                                              \
  -CFLAGS "-DTOPLEVEL_NAME=ara_tb_verilator"                                        \
  -CFLAGS "-DNR_LANES=4"                                              \
  -CFLAGS -I/home/hpc-user/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp       \
  -CFLAGS -I/home/hpc-user/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp \
  -CFLAGS -I/home/hpc-user/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp \
  ""                                                             \
  -LDFLAGS "-lelf"                                                              \
  ""                                                              \
  --exe                                                                         \
  /home/hpc-user/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp/*.cc            \
  /home/hpc-user/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp/*.cc      \
  /home/hpc-user/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/*.cc      \
  /home/hpc-user/ara/hardware/tb/verilator/ara_tb.cpp                                           \
  --cc                                                                          \
  --top-module ara_tb_verilator &&                                                  \
cd build/verilator && OBJCACHE='' make -j4 -f Vara_tb_verilator.mk
%Error: Verilator internal fault, sorry. Suggest trying --debug --gdbbt
%Error: Command Failed /home/hpc-user/ara/install/verilator/bin/verilator_bin -f build/verilator/bender_script_default -GNrLanes=4 -O3 -Wno-BLKANDNBLK -Wno-CASEINCOMPLETE -Wno-CMPCONST -Wno-LATCH -Wno-LITENDIAN -Wno-UNOPTFLAT -Wno-UNPACKED -Wno-UNSIGNED -Wno-WIDTH -Wno-WIDTHCONCAT --hierarchical tb/verilator/waiver.vlt --Mdir build/verilator -Itb/dpi --compiler clang -CFLAGS -DTOPLEVEL_NAME=ara_tb_verilator -CFLAGS -DNR_LANES=4 -CFLAGS -I/home/hpc-user/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp -CFLAGS -I/home/hpc-user/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp -CFLAGS -I/home/hpc-user/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp  -LDFLAGS -lelf  --exe /home/hpc-user/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp/dpi_memutil.cc /home/hpc-user/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp/sv_scoped.cc /home/hpc-user/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp/verilator_memutil.cc /home/hpc-user/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/verilated_toplevel.cc /home/hpc-user/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/verilator_sim_ctrl.cc /home/hpc-user/ara/hardware/tb/verilator/ara_tb.cpp --cc --top-module ara_tb_verilator
make: *** [Makefile:146: build/verilator/Vara_tb_verilator] Error 255

The version of the Verilator is 4.210.

Currently Ara works in the bare metal mode. So to support virtual memory and Linux in Ara, we need:

• TLB logic in Ara (addrgen module?)
• TLB miss handling-page walk
• TLB shootdown mechanism
• Page fault (and interrupt?) handling (Based on the RISC-V vector spec, precise exceptions are required for virtual memory support)
• Context switching

fail information:
In file included from ../V3Combine.cpp:27:
../V3DupFinder.h:50:5: error: constructor for 'V3DupFinder' must explicitly initialize the const member 'm_hasher'
V3DupFinder(){};
^
../V3DupFinder.h:46:20: note: 'm_hasher' declared here
const V3Hasher m_hasher;
^
1 error generated.
../Makefile_obj:297: recipe for target 'V3Combine.o' failed
make[3]: *** [V3Combine.o] Error 1

But if i del "CC=$(CLANG_CC) CXX=$(CLANG_CXX) CXXFLAGS=$(CLANG_CXXFLAGS) LDFLAGS=$(CLANG_LDFLAGS) " this, all version of verilator can compile succeed!

Best Wishes!

ara/hardware$ make verilate
Makefile:43: "Specified QuestaSim version (questa-2020.1) not found in PATH /usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin:/opt/riscv/bin:/opt/symbioticeda/bin"
rm -rf build/verilator; mkdir -p build/verilator
./bender script verilator -t rtl -t ara_test -t cva6_test -t verilator --define NR_LANES=4 --define VLEN=4096 --define RVV_ARIANE=1 > build/verilator/bender_script
/home/con/Desktop/ARA_/ara/install/verilator/bin/verilator -f build/verilator/bender_script                     \
  -GNrLanes=4                                                         \
  -O3                                                                           \
  -Wno-BLKANDNBLK                                                               \
  -Wno-CASEINCOMPLETE                                                           \
  -Wno-CMPCONST                                                                 \
  -Wno-LITENDIAN                                                                \
  -Wno-MODDUP                                                                   \
  -Wno-PINMISSING                                                               \
  -Wno-SYMRSVDWORD                                                              \
  -Wno-UNOPTFLAT                                                                \
  -Wno-UNPACKED                                                                 \
  -Wno-UNSIGNED                                                                 \
  -Wno-WIDTH                                                                    \
  -Wno-WIDTHCONCAT                                                              \
  --Mdir build/verilator --trace                                               \
  -Itb/dpi                                                                      \
  -CFLAGS "-std=c++11 -Wall -DTOPLEVEL_NAME=ara_tb_verilator"                       \
  -CFLAGS "-DNR_LANES=4"                                              \
  -CFLAGS -I/home/con/Desktop/ARA_/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp       \
  -CFLAGS -I/home/con/Desktop/ARA_/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp \
  -CFLAGS -I/home/con/Desktop/ARA_/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp \
  -LDFLAGS "-lelf"                                                              \
  --exe                                                                         \
  /home/con/Desktop/ARA_/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp/*.cc            \
  /home/con/Desktop/ARA_/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp/*.cc      \
  /home/con/Desktop/ARA_/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/*.cc      \
  /home/con/Desktop/ARA_/ara/hardware/tb/verilator/ara_tb.cpp                                           \
  --cc                                                                          \
  --top-module ara_tb_verilator &&                                                  \
cd build/verilator && OBJCACHE='' make -j4 -f Vara_tb_verilator.mk

Killed
%Error: Command Failed /home/con/Desktop/ARA_/ara/install/verilator/bin/verilator_bin -f build/verilator/bender_script -GNrLanes\=4 -O3 -Wno-BLKANDNBLK -Wno-CASEINCOMPLETE -Wno-CMPCONST -Wno-LITENDIAN -Wno-MODDUP -Wno-PINMISSING -Wno-SYMRSVDWORD -Wno-UNOPTFLAT -Wno-UNPACKED -Wno-UNSIGNED -Wno-WIDTH -Wno-WIDTHCONCAT --Mdir build/verilator --trace -Itb/dpi -CFLAGS -std\=c\+\+11\ -Wall\ -DTOPLEVEL_NAME\=ara_tb_verilator -CFLAGS -DNR_LANES\=4 -CFLAGS -I/home/con/Desktop/ARA_/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp -CFLAGS -I/home/con/Desktop/ARA_/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp -CFLAGS -I/home/con/Desktop/ARA_/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp -LDFLAGS -lelf --exe /home/con/Desktop/ARA_/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp/dpi_memutil.cc /home/con/Desktop/ARA_/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp/sv_scoped.cc /home/con/Desktop/ARA_/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp/verilator_memutil.cc /home/con/Desktop/ARA_/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/verilated_toplevel.cc /home/con/Desktop/ARA_/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/verilator_sim_ctrl.cc /home/con/Desktop/ARA_/ara/hardware/tb/verilator/ara_tb.cpp --cc --top-module ara_tb_verilator
Makefile:125: recipe for target 'build/verilator/Vara_tb_verilator' failed
make: *** [build/verilator/Vara_tb_verilator] Error 137

Currently, Ara supports the most important FP operations to run a matmul kernel.
All the other vector floating-point instructions still need to be added.

Note:
Some of them, namely:

• vfclass
• vfdiv
• vfsqrt

are not implemented due to issues with the FPU (fpnew) when operating in vectorial (SIMD) mode. Once these problems are solved, the corresponding instructions will be added as well.

Hi,
The ligloss library cannot be found when compiling hello_world. When I add the tool chain install directory to the path, the same problem still exists.
root@zte-R5300-G4-riscv:/share/zhuxuanlong/Vector_Work/ara/apps# make bin/hello_world chmod +x /share/zhuxuanlong/Vector_Work/ara/apps/common/script/align_sections.sh rm -f /share/zhuxuanlong/Vector_Work/ara/apps/common/link.ld && cp /share/zhuxuanlong/Vector_Work/ara/apps/common/arch.link.ld /share/zhuxuanlong/Vector_Work/ara/apps/common/link.ld /share/zhuxuanlong/Vector_Work/ara/apps/common/script/align_sections.sh 4 /share/zhuxuanlong/Vector_Work/ara/apps/common/link.ld /share/zhuxuanlong/Vector_Work/ara/install/riscv-llvm/bin/clang -march=rv64gcv0p10 -mabi=lp64d -menable-experimental-extensions -mno-relax -fuse-ld=lld -mcmodel=medany -I/share/zhuxuanlong/Vector_Work/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf -DNR_LANES=4 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument -c hello_world/main.c -o hello_world/main.c.o /share/zhuxuanlong/Vector_Work/ara/install/riscv-llvm/bin/clang -march=rv64gcv0p10 -mabi=lp64d -menable-experimental-extensions -mno-relax -fuse-ld=lld -mcmodel=medany -I/share/zhuxuanlong/Vector_Work/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf -DNR_LANES=4 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument -c common/crt0.S -o common/crt0-llvm.S.o /share/zhuxuanlong/Vector_Work/ara/install/riscv-llvm/bin/clang -march=rv64gcv0p10 -mabi=lp64d -menable-experimental-extensions -mno-relax -fuse-ld=lld -mcmodel=medany -I/share/zhuxuanlong/Vector_Work/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf -DNR_LANES=4 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument -c common/printf.c -o common/printf-llvm.c.o /share/zhuxuanlong/Vector_Work/ara/install/riscv-llvm/bin/clang -march=rv64gcv0p10 -mabi=lp64d -menable-experimental-extensions -mno-relax -fuse-ld=lld -mcmodel=medany -I/share/zhuxuanlong/Vector_Work/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf -DNR_LANES=4 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument -c common/string.c -o common/string-llvm.c.o /share/zhuxuanlong/Vector_Work/ara/install/riscv-llvm/bin/clang -march=rv64gcv0p10 -mabi=lp64d -menable-experimental-extensions -mno-relax -fuse-ld=lld -mcmodel=medany -I/share/zhuxuanlong/Vector_Work/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf -DNR_LANES=4 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument -c common/serial.c -o common/serial-llvm.c.o mkdir -p bin/ /share/zhuxuanlong/Vector_Work/ara/install/riscv-llvm/bin/clang -Iinclude -march=rv64gcv0p10 -mabi=lp64d -menable-experimental-extensions -mno-relax -fuse-ld=lld -mcmodel=medany -I/share/zhuxuanlong/Vector_Work/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf -DNR_LANES=4 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument -o bin/hello_world hello_world/main.c.o common/crt0-llvm.S.o common/printf-llvm.c.o common/string-llvm.c.o common/serial-llvm.c.o -static -nostartfiles -lm -T/share/zhuxuanlong/Vector_Work/ara/apps/common/link.ld ld.lld: error: unable to find library -lgloss clang-13: error: ld command failed with exit code 1 (use -v to see invocation) make: *** [Makefile:59: bin/hello_world] Error 1 rm hello_world/main.c.o common/string-llvm.c.o common/crt0-llvm.S.o common/printf-llvm.c.o common/serial-llvm.c.o

Thank you.

Excuse me：
I want to implement ARA on FPGA，So I put ARA relevant RTL files into Vivado。
I amend "parameter int unsigned NrLanes = 2," the parameter in ara_soc.sv files and "localparam int unsigned VLEN = 4096;//ifdef VLEN VLEN else 0 endif;" in ara_pkg.sv files.The Vivado show error "Cannot support half-precision floating-point on Ara if Ariane does not support it." I want to why?

Best Wishes!

I changed nr_lanes in config/config.mk to 8, but when i ran make verilate, i got the following error :

so did the combination of nr_lanes=8 and vlen=4096 tested ? and are there any usable combinations except na_lanes=4 and vlen=4096 ?

I am unable to build the toolchain with the Makefile. Here is the error log:

mkdir -p /users/hemmat/MyRepos/ara/install/riscv-gcc
# Apply patch on riscv-binutils
cd /users/hemmat/MyRepos/ara/toolchain/riscv-gnu-toolchain/riscv-binutils && git reset --hard && git apply /users/hemmat/MyRepos/ara/patches/0001-riscv-binutils-patch
HEAD is now at c5ef83e Revert "Change the return type of `match_func` and `constraints` flag to `bfd_boolean`."
cd /users/hemmat/MyRepos/ara/toolchain/riscv-gnu-toolchain && rm -rf build && mkdir -p build && cd build && \
CC=gcc-7.2.0 CXX=g++-7.2.0 ../configure --prefix=/users/hemmat/MyRepos/ara/install/riscv-gcc --with-arch=rv64gcv --with-cmodel=medlow --enable-multilib && \
make MAKEINFO=true -j4
checking for gcc... gcc-7.2.0
checking whether the C compiler works... no
configure: error: in `/users/hemmat/MyRepos/ara/toolchain/riscv-gnu-toolchain/build':
configure: error: C compiler cannot create executables
See `config.log' for more details
make: *** [/users/hemmat/MyRepos/ara/install/riscv-gcc] Error 77

It looks like by default you are expecting the user to have gcc-7.2.0 which is set here:

I propose to use only gcc and g++ without any specific version attach to it. Refer to this PR: #25

Reminder issue

emul checks are done using ara_req_d.emul. This is not correct if one of the source operands has different emul w.r.t. the other source or destination register.
Easy fix: introduce other internal emul signals to differentiate the emul checks on the single registers (no need for dispatching these signals to the sequencer).

Hi, @mp-17 @suehtamacv
When I try to make riscv_tests_simv according to the README file, my terminal has been stuck with no message update for a long while, about a few hours.

(base) ➜ hardware git:(main) ✗ make riscv_tests_simv
build/verilator/Vara_tb_verilator -l ram,/home/fantasysee/Projects/ara/apps/bin/rv64uv-ara-vadd,elf &> build/rv64uv-ara-vadd.trace

And I checked the message in the build/rv64uv-ara-vadd.trace file for several times, which is listed as below. It remains the same for a long while as well.

Program header number 0 in `/home/fantasysee/Projects/ara/apps/bin/rv64uv-ara-vadd' low is 80000000
Program header number 0 in `/home/fantasysee/Projects/ara/apps/bin/rv64uv-ara-vadd' high is 80004179
Program header number 1 in `/home/fantasysee/Projects/ara/apps/bin/rv64uv-ara-vadd' high is 80004877
Program header number 2 in `/home/fantasysee/Projects/ara/apps/bin/rv64uv-ara-vadd' high is 80004b17
Program header number 3 in `/home/fantasysee/Projects/ara/apps/bin/rv64uv-ara-vadd' is not of type PT_LOAD; ignoring.
Set `ram TOP.ara_tb_verilator.dut.i_ara_soc.i_dram 10 0x80000000 0x80000 write with offset: 0x0 write with size: 0x4b18
Simulation of Ara
=================


Simulation running, end by pressing CTRL-c.

Note that, my QuestaSim version is Mentor Graphics QuestaSim 10.6c instead of Mentor Graphics QuestaSim 2020.1. And I merely make a fake version soft link to 2020.1, with no modification in the hardware/Makefile.

Is this experimental phenomenon normal? If yes, could you please tell me how long this process approximately lasts? If no, would you please help me check if there is something wrong with my experimental environment?

Thanks in advance!!!

Write requests from SLDU/MASKU/VLSU have low priority wrt requests from the computational FUs and operand queues. The request of one of the low priority units to the operand requesters is buffered into a stream register (FIFO). The request is granted by default if the FIFO is not full. But the actual VRF write can be delayed indefinitely if higher priority requests are made to the same VRF bank. This leads to RAW constraints violations, as the early grant unset the instruction ID from the running instructions, also clearing the hazards bits of the dependant instructions that are free to execute, possibly fetching their operand before the write of the low priority request occurs.

Here a little example:

0: vslide1down X, Y
1: vfmul Z, X

The vfmul gets the hazard bit on instruction 0 and stalls, waiting for 0 to write X. The sldu fires a request to the operand requesters, and it immediately gets the gnt from the stream registers (the gnt is always asserted). The problem is that the real request to the VRF is not done, and it is not sure when it will happen (because of the priority arbiters; e.g., our request is delayed because a VFMUL is reading from bank 0, another VFMUL wants to write in bank0, interleaved). In the meantime, the sldu received the grant, so it tells the main sequencer that its instruction is over. So the hazards bits for the vfmul are cleared, and the vfmul can violate the RAW hazard if the write by the slide unit did not happen.

We need to set-up a CI for Ara, using GitHub Actions.

When I try to make verilator according to the README file, I face this error:

$ make verilator 
# Checkout the right version
cd /home/hpc-user/ara/toolchain/verilator && git reset --hard && git fetch && git checkout v4.210
HEAD is now at 8e2ba6a0 Version bump
HEAD is now at 8e2ba6a0 Version bump
# Compile verilator
cd /home/hpc-user/ara/toolchain/verilator && git clean -xfdf && autoconf && \
CC=clang CXX=clang++ CXXFLAGS="" LDFLAGS="" \
	./configure --prefix=/home/hpc-user/ara/install/verilator && make -j8 && make install
Removing autom4te.cache/
Removing config.log
Removing configure
configuring for Verilator 4.210 2021-07-07
checking whether to perform partial static linking of Verilator binary... yes
checking whether to use tcmalloc... check
checking whether to use -m32... no
checking whether to build for coverage collection... no
checking whether to use hardcoded paths... yes
checking whether to show and stop on compilation warnings... no
checking whether to run long tests... no
checking for gcc... clang
checking whether the C compiler works... no
configure: error: in `/home/hpc-user/ara/toolchain/verilator':
configure: error: C compiler cannot create executables
See `config.log' for more details
make: *** [Makefile:144: /home/hpc-user/ara/install/verilator] Error 77

Here is the error I face in the config.log:

configure:2647: clang -V >&5
clang-13: error: argument to '-V' is missing (expected 1 value)
clang-13: error: no input files
configure:2658: $? = 1
configure:2647: clang -qversion >&5
clang-13: error: unknown argument '-qversion'; did you mean '--version'?
clang-13: error: no input files
configure:2658: $? = 1
configure:2678: checking whether the C compiler works
configure:2700: clang       conftest.c  >&5
ld.lld: error: unable to find library -lc
ld.lld: error: unable to find library -lm
ld.lld: error: unable to find library -lclang_rt.builtins-riscv64
clang-13: error: ld.lld command failed with exit code 1 (use -v to see invocation)
configure:2704: $? = 1
configure:2742: result: no
configure: failed program was:
| /* confdefs.h */
| #define PACKAGE_NAME "Verilator"
| #define PACKAGE_TARNAME "verilator"
| #define PACKAGE_VERSION "4.210 2021-07-07"
| #define PACKAGE_STRING "Verilator 4.210 2021-07-07"
| #define PACKAGE_BUGREPORT "https://verilator.org"
| #define PACKAGE_URL "https://verilator.org"
| #define PACKAGE_VERSION_NUMBER_STRING "4.210"
| /* end confdefs.h.  */
| 
| int
| main ()
| {
| 
|   ;
|   return 0;
| }
configure:2747: error: in `/home/hpc-user/ara/toolchain/verilator':
configure:2749: error: C compiler cannot create executables
See `config.log' for more details

The RISC-V community is working on instrinsics to ease the C-level programmability: https://github.com/riscv/rvv-intrinsic-doc.
The related branch of the riscv-toolchain (rvv-intrinsic, https://github.com/riscv/riscv-gnu-toolchain/tree/rvv-intrinsic) produces code compliant with the version 0.10 of the specs.
To support the intrinsics, we need to:

• Update SPIKE
• Update the toolchain
• Update Ara (#1)

The following operation does not work on Ara.

VSET(1, e64, m1);
VLOAD_64(v1, 0xffffffffffffffff);
VSET(16, e16, m1);
VLOAD_16(v2, 0x33ca, ..., 0x314f);
VLOAD_16(v3, 0x33ca, ..., 0xbb98);
asm volatile("vmfeq.vv v1, v2, v3");
VSET(1, e64, m1);
VCMP_U64(13, v1, 0xffffffffffff0001);

The same register is first loaded with one 64-bit element, and then a 16 bits mask is produced from a e16 comparison. The final store operation de-shuffles the VRF elements as the register hosted e16 data. The problem is that the mask unit does not store the mask results following a e16 shuffled pattern, and does not re-shuffle the previously held e64 element into e16 elements.

Potentially, the issue is broader:
Ara can have problems with multiple operations on the same register if VSEW [and vl] are changed, as not all the elements are re-shuffled during the second operation. Part of the old elements remains shuffled in the register (check this, and open another issue if true). If this is the case, when there is a change in VSEW, the previously held elements must be re-shuffled with the correct VSEW.

Ara depends on a patched version of CVA6, which was forked from the official version into the pulp-platform organization.

We should use the official CVA6 repository instead, once the PRs have been merged.

In may network, we can not access this kind of url like: "git clone git://git. ....", since this is old format of github url, we suggest it to http format.

ara/Makefile line 131 "git clone git://git.kernel.org/pub/scm/utils/dtc/dtc.git" changing to "git clone https://git.kernel.org/pub/scm/utils/dtc/dtc.git" will be better, since this is the github's offical format.

Best Wishes

I am trying to run makefile target make verilate but I am getting the following errors on the default settings.

$ make verilate 
Makefile:43: "Specified QuestaSim version (questa-2020.1) not found in PATH 
rm -rf build/verilator; mkdir -p build/verilator
./bender script verilator -t rtl -t ara_test -t cva6_test -t verilator --define NR_LANES=4 --define VLEN=4096 --define RVV_ARIANE=1 > build/verilator/bender_script
/home/ara/install/verilator/bin/verilator -f build/verilator/bender_script                     \
  -GNrLanes=4                                                         \
  -O3                                                                           \
  -Wno-BLKANDNBLK                                                               \
  -Wno-CASEINCOMPLETE                                                           \
  -Wno-CMPCONST                                                                 \
  -Wno-LITENDIAN                                                                \
  -Wno-MODDUP                                                                   \
  -Wno-PINMISSING                                                               \
  -Wno-SYMRSVDWORD                                                              \
  -Wno-UNOPTFLAT                                                                \
  -Wno-UNPACKED                                                                 \
  -Wno-UNSIGNED                                                                 \
  -Wno-WIDTH                                                                    \
  -Wno-WIDTHCONCAT                                                              \
  --Mdir build/verilator --trace                                               \
  -Itb/dpi                                                                      \
  -CFLAGS "-std=c++11 -Wall -DTOPLEVEL_NAME=ara_tb_verilator"                       \
  -CFLAGS "-DNR_LANES=4"                                              \
  -CFLAGS -I/home/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp       \
  -CFLAGS -I/home/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp \
  -CFLAGS -I/home/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp \
  -LDFLAGS "-lelf"                                                              \
  --exe                                                                         \
  /home/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp/*.cc            \
  /home/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp/*.cc      \
  /home/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/*.cc      \
  /home/ara/hardware/tb/verilator/ara_tb.cpp                                           \
  --cc                                                                          \
  --top-module ara_tb_verilator &&                                                  \
cd build/verilator && OBJCACHE='' make -j4 -f Vara_tb_verilator.mk
%Error: /home/ara/hardware/deps/tech_cells_generic/src/rtl/tc_sram.sv:93:38: Unsupported or unknown PLI call: $urandom
   93 |           "random": init_val[i][j] = $urandom();
      |                                      ^~~~~~~~
%Error: /home/ara/hardware/tb/ara_tb.sv:30:28: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER
   30 |   localparam ClockPeriod = 1ns;
      |                            ^~~
%Warning-STMTDLY: /home/ara/hardware/tb/ara_tb.sv:48:10: Unsupported: Ignoring delay on this delayed statement.
   48 |   always #(ClockPeriod/2) clk = !clk;
      |          ^
                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.
%Warning-STMTDLY: /home/ara/hardware/tb/ara_tb.sv:56:7: Unsupported: Ignoring delay on this delayed statement.
   56 |       #(ClockPeriod);
      |       ^
%Warning-STMTDLY: /home/ara/hardware/tb/ara_tb.sv:98:7: Unsupported: Ignoring delay on this delayed statement.
   98 |       #ClockPeriod;
      |       ^
%Error: Exiting due to 2 error(s), 3 warning(s)
        ... See the manual and https://verilator.org for more assistance.
Makefile:123: recipe for target 'build/verilator/Vara_tb_verilator' failed
make: *** [build/verilator/Vara_tb_verilator] Error 1

What could be the possible cause for that?

Changing .gitmodules line 29 from "url = git://sourceware.org/git/newlib-cygwin.git" to "url = https://sourceware.org/git/newlib-cygwin.git" can fix this bug!

Best Wishes!

function automatic vfu_e vfu(ara_op_e op);
unique case (op) inside
[VADD :VMERGE ]: vfu = VFU_Alu ;
[VMUL :VFCVTFF ]: vfu = VFU_MFpu ;
[VMFEQ :VMXNOR ]: vfu = VFU_MaskUnit ;
[VLE :VLXE ]: vfu = VFU_LoadUnit ;
[VSE :VSXE ]: vfu = VFU_StoreUnit;
[VSLIDEUP:VSLIDEDOWN]: vfu = VFU_SlideUnit;
endcase
endfunction : vfu
Verilator does not suport "[VADD :VMERGE ]" this format, so the function vfu can simply change to:
function automatic vfu_e vfu(ara_op_e op);
if((VADD <= op) && (op <= VMERGE )) begin vfu = VFU_Alu ; end
if((VMUL <= op) && (op <= VFCVTFF )) begin vfu = VFU_MFpu ; end
if((VMFEQ <= op) && (op <= VMXNOR )) begin vfu = VFU_MaskUnit ; end
if((VLE <= op) && (op <= VLXE )) begin vfu = VFU_LoadUnit ; end
if((VSE <= op) && (op <= VSXE )) begin vfu = VFU_StoreUnit; end
if((VSLIDEUP <= op) && (op <= VSLIDEDOWN)) begin vfu = VFU_SlideUnit; end
endfunction : vfu

After this change the code can be compiled by verilator (Default Setting).

Best Wishes!

version: main branch from Oct. 1st.

From the https://github.com/pulp-platform/ara/blob/main/FUNCTIONALITIES.md file, vmv instructions are supported, but a test shows this seems only refering to vmv.v.* instructions, not the single element move instructions?

A very common use case is to build up a list of values from scalar computation and shift those values one by one into vector registers. Without this instruction, a few more instructions would be needed to build up a mask and then use vmv.v.* instruction, however vmv.v.* instructions are encoded as unmasked instructions so this essentially cannot be done.

Thanks.

I follow the guideline in README, and when I go to step
make riscv_tests

it seems that I need to make toolchain-gcc first

when I make toolchian-gcc, another problem comes

the log shows several similar errors like this "cannot stat 'xxx.gmo': No such file or directory"

How should I solve this problem?

The following example runs smoothly on SPIKE, but it is not correctly handled by Ara.

void TEST_CASE5(void) {
  int64_t zero = 0;
  VSET(2, e64, m1);
  VLOAD_64(v0, 0x76543210fedcba98, 0x76543210fedcba98);
  VSET(2, e16, m1);
  asm volatile("vmul.vx v0, v0, %[A]" :: [A] "r"(zero));
  VCMP_U64(13, v0, 0x7654321000000000, 0x76543210fedcba98);
};

If we change EEW but we do not reshuffle the previous content before writing, the previous information is corrupted.

Through reading makefie, I found that your default simulation tool is questasim 2020.1, but for some reasons, I only have version 10.4 of the simulation tool. Can I simulate a lower version than 2020?
Thanks.

I hit a verilator error while working on the latest ara code base, and this is different from the other closed verilator issues.

patch is applied with:

$ make apply-patches
Verilator version are the same as specified in top level Makefile:

../install/verilator/bin/verilator --version
Verilator 4.210 2021-07-07 rev v4.210

 $ make verilate
Makefile:62: "Specified QuestaSim version (questa-2020.1) not found in PATH /home/yanghao/.local/bin:/home/yanghao/bin:/usr/local/cuda-11.1/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin:/home/yanghao/bin"
rm -rf build/verilator; mkdir -p build/verilator
./bender script verilator -t rtl -t ara_test -t cva6_test -t verilator --define NR_LANES=4 --define VLEN=4096 --define RVV_ARIANE=1 > build/verilator/bender_script_default
/mnt/work/yanghao/pulp/ara/install/verilator/bin/verilator -f build/verilator/bender_script_default           \
  -GNrLanes=4                                                         \
  -O3                                                                           \
  -Wno-BLKANDNBLK                                                               \
  -Wno-CASEINCOMPLETE                                                           \
  -Wno-CMPCONST                                                                 \
  -Wno-LATCH                                                                    \
  -Wno-LITENDIAN                                                                \
  -Wno-UNOPTFLAT                                                                \
  -Wno-UNPACKED                                                                 \
  -Wno-UNSIGNED                                                                 \
  -Wno-WIDTH                                                                    \
  -Wno-WIDTHCONCAT                                                              \
  --hierarchical                                                                \
  tb/verilator/waiver.vlt                                                       \
  --Mdir build/verilator                                                       \
  -Itb/dpi                                                                      \
  --compiler clang                                                              \
  -CFLAGS "-DTOPLEVEL_NAME=ara_tb_verilator"                                        \
  -CFLAGS "-DNR_LANES=4"                                              \
  -CFLAGS -I/mnt/work/yanghao/pulp/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp       \
  -CFLAGS -I/mnt/work/yanghao/pulp/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp \
  -CFLAGS -I/mnt/work/yanghao/pulp/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp \
  ""                                                             \
  -LDFLAGS "-lelf"                                                              \
  ""                                                              \
  --exe                                                                         \
  /mnt/work/yanghao/pulp/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp/*.cc            \
  /mnt/work/yanghao/pulp/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp/*.cc      \
  /mnt/work/yanghao/pulp/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/*.cc      \
  /mnt/work/yanghao/pulp/ara/hardware/tb/verilator/ara_tb.cpp                                           \
  --cc                                                                          \
  --top-module ara_tb_verilator &&                                                  \
cd build/verilator && OBJCACHE='' make -j4 -f Vara_tb_verilator.mk
%Error-PKGNODECL: /mnt/work/yanghao/pulp/ara/hardware/deps/axi/src/axi_dw_downsizer.sv:56:10: Package/class 'cf_math_pkg' not found, and needs to be predeclared (IEEE 1800-2017 26.3)
   56 |   import cf_math_pkg::idx_width;
      |          ^~~~~~~~~~~
                  ... For error description see https://verilator.org/warn/PKGNODECL?v=4.210
%Error: /mnt/work/yanghao/pulp/ara/hardware/deps/axi/src/axi_dw_downsizer.sv:56:10: Importing from missing package 'cf_math_pkg'
   56 |   import cf_math_pkg::idx_width;
      |          ^~~~~~~~~~~
%Error: /mnt/work/yanghao/pulp/ara/hardware/deps/axi/src/axi_dw_upsizer.sv:56:10: Importing from missing package 'cf_math_pkg'
   56 |   import cf_math_pkg::idx_width;
      |          ^~~~~~~~~~~
%Error: /mnt/work/yanghao/pulp/ara/hardware/deps/cva6/src/acc_dispatcher.sv:51:10: Importing from missing package 'cf_math_pkg'
   51 |   import cf_math_pkg::idx_width;
      |          ^~~~~~~~~~~
%Error: /mnt/work/yanghao/pulp/ara/hardware/src/lane/lane_sequencer.sv:11:68: Importing from missing package 'cf_math_pkg'
   11 | module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::idx_width; #(
      |                                                                    ^~~~~~~~~~~
%Error: /mnt/work/yanghao/pulp/ara/hardware/src/lane/operand_queue.sv:11:67: Importing from missing package 'cf_math_pkg'
   11 | module operand_queue import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::idx_width; #(
      |                                                                   ^~~~~~~~~~~
%Error: /mnt/work/yanghao/pulp/ara/hardware/src/lane/operand_requester.sv:75:10: Importing from missing package 'cf_math_pkg'
   75 |   import cf_math_pkg::idx_width;
      |          ^~~~~~~~~~~
%Error: /mnt/work/yanghao/pulp/ara/hardware/src/masku/masku.sv:46:10: Importing from missing package 'cf_math_pkg'
   46 |   import cf_math_pkg::idx_width;
      |          ^~~~~~~~~~~
%Error: /mnt/work/yanghao/pulp/ara/hardware/src/sldu/sldu.sv:41:10: Importing from missing package 'cf_math_pkg'
   41 |   import cf_math_pkg::idx_width;
      |          ^~~~~~~~~~~
%Error: /mnt/work/yanghao/pulp/ara/hardware/src/vlsu/addrgen.sv:47:10: Importing from missing package 'cf_math_pkg'
   47 |   import cf_math_pkg::ceil_div;
      |          ^~~~~~~~~~~
%Error: /mnt/work/yanghao/pulp/ara/hardware/src/vlsu/vldu.sv:52:10: Importing from missing package 'cf_math_pkg'
   52 |   import cf_math_pkg::idx_width;
      |          ^~~~~~~~~~~
%Error: /mnt/work/yanghao/pulp/ara/hardware/src/vlsu/vstu.sv:60:10: Importing from missing package 'cf_math_pkg'
   60 |   import cf_math_pkg::idx_width;
      |          ^~~~~~~~~~~
%Error: /mnt/work/yanghao/pulp/ara/hardware/src/lane/valu.sv:46:10: Importing from missing package 'cf_math_pkg'
   46 |   import cf_math_pkg::idx_width;
      |          ^~~~~~~~~~~
%Error: /mnt/work/yanghao/pulp/ara/hardware/src/lane/vmfpu.sv:48:10: Importing from missing package 'cf_math_pkg'
   48 |   import cf_math_pkg::idx_width;
      |          ^~~~~~~~~~~
%Error: /mnt/work/yanghao/pulp/ara/hardware/src/ara.sv:48:10: Importing from missing package 'cf_math_pkg'
   48 |   import cf_math_pkg::idx_width;
      |          ^~~~~~~~~~~
%Error: Exiting due to 15 error(s)
        ... See the manual at https://verilator.org/verilator_doc.html for more assistance.
make: *** [Makefile:146: build/verilator/Vara_tb_verilator] Error 1

The FPU uses special signals called tag_i and tag_o to track the ongoing operations. They are required since the latency of the various FPU blocks is not the same, and some operations can overtake the previous ones so that the results are produced out-of-order.
We must enforce an in-order production of results.

I look at spec0.9, and the description of mapping seems to be a little different from your official one. Specifically when sew = 16 and sew = 8.

At the same time, ask a question. After version 1.0, slen was deleted, and mapping was different. This kind of mapping seems to be more complicated.

One of the ways in which Ara is currently verified is by running rv64uv tests following the riscv-tests approach (https://github.com/riscv/riscv-tests), i.e., verifying each instruction with ad-hoc tests exploiting common macros.

The riscv-tests are just a primer and do not exhaustively verify the design functionality under different combinations of parameters (vl, vstart, ...) and instruction intermixes. This should be addressed with specific tests.

When vl = 0, vector loads do not work as expected and generate undefined behaviour.

Hello.

I tried to follow the guideline for viewing signal waveforms described in the README file.
The make verilate trace=1 works fine, but the app=<APP> make simv trace=1 throws a "segmentation fault" error. This happens even when <APP> is hello_world.

This is the exact error I get after the Simulation of Ara line:

Simulation of Ara
=================

Tracing can be toggled by sending SIGUSR1 to this process:
$ kill -USR1 408c
Makefile:187: recipe for target 'simv' failed
make: *** [simv] Segmentation fault (core dumped)

Thank you in advance.

Once the RISC-V GCC toolchain and the Spike simulator have been updated to version 0.10, the same can be done with Ara.

In terms of microarchitectural changes, RVV 0.10 deprecates the SLEN parameter, the striping distance being set as being always equal to the vector length VLEN. Current Ara already takes this into account, since it considers that SLEN = VLEN.

Other RVV-upgrade changes include the implementation of extra floating-point instructions, and encoding changes with a few vector CSRs.

The LMUL value imposes some constraints on the registers that can be used as operands/destination. Widening instructions can have mixed widths, and the restrictions can vary from one operand/destination register to the other.
Currently, the LMUL value is checked once in the dispatcher, and instructions like

vfwadd.vv v4, v2, v3

are considered illegal when LMUL = 1 due to the v3 source operand, even if they are legal.

Excuse me, do you have plans to release a fpga example project? This can actually run more programs better than simulation. cva
6 has related FPGA projects, but you seem to use many other peripheral ips.

One of the ways in which Ara is currently verified and benchmarked is by running small programs/kernels like the integer and floating-point matmul.
The kernel pool needs to be expanded to cover more use-cases. We plan to add an image convolution (conv2d) test soon.

We saw the same program (binary) runs fine on 8 and 16 lanes configuration, however hangs when running on 2 lanes or 4 lanes configuration. From the waveform, when it hangs the PC stopped moving forward. And it is not introduced by any particular vector instruction, it seems to be a mix of scalar and vector instructions that is causing this hang. Tested on latest commits and showing also the same result.

Just wondering if this is a known issue, and do you need a minimum sequence that can reproduce this issue?

make bin/hello_world, ctype.h not found ?

This is the score of Dhrystone and Coremark. Is this expected?

DMIPS_Per_MHz: 0.981
CoreMark/MHz: 1.368339

Simulation of Ara
=================


Simulation running, end by pressing CTRL-c.

Dhrystone Benchmark, Version 2.1 (Language: C)

Program compiled without 'register' attribute

Please give the number of runs through the benchmark: 
Execution starts, 100 runs through Dhrystone
Execution ends

Final values of the variables used in the benchmark:

Int_Glob:            5
        should be:   5
Bool_Glob:           1
        should be:   1
Ch_1_Glob:           A
        should be:   A
Ch_2_Glob:           B
        should be:   B
Arr_1_Glob[8]:       7
        should be:   7
Arr_2_Glob[8][7]:    110
        should be:   Number_Of_Runs + 10
Ptr_Glob->
  Ptr_Comp:          -2147473472
        should be:   (implementation-dependent)
  Discr:             0
        should be:   0
  Enum_Comp:         2
        should be:   2
  Int_Comp:          17
        should be:   17
  Str_Comp:          DHRYSTONE PROGRAM, SOME STRING
        should be:   DHRYSTONE PROGRAM, SOME STRING
Next_Ptr_Glob->
  Ptr_Comp:          -2147473472
        should be:   (implementation-dependent), same as above
  Discr:             0
        should be:   0
  Enum_Comp:         1
        should be:   1
  Int_Comp:          18
        should be:   18
  Str_Comp:          DHRYSTONE PROGRAM, SOME STRING
        should be:   DHRYSTONE PROGRAM, SOME STRING
Int_1_Loc:           5
        should be:   5
Int_2_Loc:           13
        should be:   13
Int_3_Loc:           7
        should be:   7
Enum_Loc:            1
        should be:   1
Str_1_Loc:           DHRYSTONE PROGRAM, 1'ST STRING
        should be:   DHRYSTONE PROGRAM, 1'ST STRING
Str_2_Loc:           DHRYSTONE PROGRAM, 2'ND STRING
        should be:   DHRYSTONE PROGRAM, 2'ND STRING

Number_Of_Runs: 100
User_Time: 57963 cycles
Dhrystones_Per_Second_Per_MHz: 1725
DMIPS_Per_MHz: 0.981
Microseconds for one run through Dhrystone: 5.796 
Dhrystones per Second:                      172523.840 

[284890] -Info: ara_tb_verilator.sv:47: Assertion failed in TOP.ara_tb_verilator: Core Test *** SUCCESS *** (tohost = 0)
- /home/kuoping/Projects/ara/hardware/tb/ara_tb_verilator.sv:50: Verilog $finish
Received $finish() from Verilog, shutting down simulation.

Simulation statistics
=====================
Executed cycles:  22c6d
Wallclock time:   38.747 s
Simulation speed: 3676.28 cycles/s (3.67628 kHz)

Simulation of Ara
=================


Simulation running, end by pressing CTRL-c.
2K performance run parameters for coremark.
CoreMark Size    : 666
Total ticks      : 3654064
Total time (secs): 0.036541
Iterations/Sec   : 136.833947
Iterations       : 5
Compiler version : GCCClang 13.0.0 (https://github.com/llvm/llvm-project.git b14c8f5f6eb96e70adb553cc8a4257524881e029)
Compiler flags   : -march=rv64gcv0p10 -mabi=lp64d -menable-experimental-extensions -mno-relax -fuse-ld=lld -mcmodel=medany -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf -DNR_LANES=4 -DVLEN=4096 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument
Memory location  : STACK
seedcrc          : 0xe9f5
[0]crclist       : 0xe714
[0]crcmatrix     : 0x1fd7
[0]crcstate      : 0x8e3a
[0]crcfinal      : 0xf24c
Correct operation validated. See README.md for run and reporting rules.
CoreMark 1.0 : 136.833947 / GCCClang 13.0.0 (https://github.com/llvm/llvm-project.git b14c8f5f6eb96e70adb553cc8a4257524881e029) -march=rv64gcv0p10 -mabi=lp64d -menable-experimental-extensions -mno-relax -fuse-ld=lld -mcmodel=medany -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf -DNR_LANES=4 -DVLEN=4096 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument / STACK
CoreMark/MHz: 1.368339
[7463656] -Info: ara_tb_verilator.sv:47: Assertion failed in TOP.ara_tb_verilator: Core Test *** SUCCESS *** (tohost = 0)
- /home/kuoping/Projects/ara/hardware/tb/ara_tb_verilator.sv:50: Verilog $finish
Received $finish() from Verilog, shutting down simulation.

Simulation statistics
=====================
Executed cycles:  38f174
Wallclock time:   1019.19 s
Simulation speed: 3661.57 cycles/s (3.66157 kHz)

There might be issues with our code compliance with lowRISC coding style guidelines. This issue tracks any possible style issues we find.

i'm trying to run make bin/hello_world, but i got the following errors:

make bin/hello_world
/home/workspace/pulp/ara_lenovo_unix/install/riscv-gcc/bin/riscv64-unknown-elf-gcc -mcmodel=medany -march=rv64gcv -mabi=lp64 -I/home/workspace/pulp/ara_lenovo_unix/apps/common -static -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf -DNR_LANES=4 -Wunused-variable -Wall -Wextra -c hello_world/main.c -o hello_world/main.c.o
/home/workspace/pulp/ara_lenovo_unix/install/riscv-gcc/bin/riscv64-unknown-elf-gcc -mcmodel=medany -march=rv64gcv -mabi=lp64 -I/home/workspace/pulp/ara_lenovo_unix/apps/common -static -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf -DNR_LANES=4 -Wunused-variable -Wall -Wextra -c common/crt0.S -o common/crt0.S.o
common/encoding.h: Assembler messages:
common/encoding.h:1: Error: unknown pseudo-op: ..' common/crt0.S:80: Error: illegal operands li t0,PMP_NAPOT|PMP_R|PMP_W|PMP_X'
common/crt0.S:92: Error: illegal operands li t0,(1<<CAUSE_LOAD_PAGE_FAULT)|(1<<CAUSE_STORE_PAGE_FAULT)|(1<<CAUSE_FETCH_PAGE_FAULT)|(1<<CAUSE_MISALIGNED_FETCH)|(1<<CAUSE_USER_ECALL)|(1<<CAUSE_BREAKPOINT)' common/crt0.S:102: Error: illegal operands li t0,(MSTATUS_FS&(MSTATUS_FS>>1))'
common/crt0.S:106: Error: illegal operands `li t0,(MSTATUS_VS&(MSTATUS_VS>>1))'
/home/workspace/pulp/ara_lenovo_unix/apps/common/runtime.mk:66: recipe for target 'common/crt0.S.o' failed
make: *** [common/crt0.S.o] Error 1
rm hello_world/main.c.o

what could be the reason for this ?

hi，I am trying to run makefile，but there were some mistakes
~/riscv/ara/hardware$ make verilate
Makefile:43: "Specified QuestaSim version (questa-2020.1) not found in PATH /home/wu/riscv/gcc/riscv-unknown-elf-gcc/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin"
rm -rf build/verilator; mkdir -p build/verilator
./bender script verilator -t rtl -t ara_test -t cva6_test -t verilator --define NR_LANES=4 --define VLEN=4096 --define RVV_ARIANE=1 > build/verilator/bender_script
/home/wu/riscv/ara/install/verilator/bin/verilator -f build/verilator/bender_script
-GNrLanes=4
-O3
-Wno-BLKANDNBLK
-Wno-CASEINCOMPLETE
-Wno-CMPCONST
-Wno-LITENDIAN
-Wno-MODDUP
-Wno-PINMISSING
-Wno-SYMRSVDWORD
-Wno-UNOPTFLAT
-Wno-UNPACKED
-Wno-UNSIGNED
-Wno-WIDTH
-Wno-WIDTHCONCAT
--Mdir build/verilator --trace
-Itb/dpi
-CFLAGS "-std=c++11 -Wall -DTOPLEVEL_NAME=ara_tb_verilator"
-CFLAGS "-DNR_LANES=4"
-CFLAGS -I/home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp
-CFLAGS -I/home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp
-CFLAGS -I/home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp
-LDFLAGS "-lelf"
--exe
/home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp/.cc
/home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp/.cc
/home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/*.cc
/home/wu/riscv/ara/hardware/tb/verilator/ara_tb.cpp
--cc
--top-module ara_tb_verilator &&
cd build/verilator && OBJCACHE='' make -j4 -f Vara_tb_verilator.mk
make[1]: Entering directory '/home/wu/riscv/ara/hardware/build/verilator'
g++ -I. -MMD -I/home/wu/riscv/ara/install/verilator/share/verilator/include -I/home/wu/riscv/ara/install/verilator/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=c++11 -Wall -DTOPLEVEL_NAME=ara_tb_verilator -DNR_LANES=4 -I/home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp -I/home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp -I/home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp -std=gnu++14 -Os -c -o ara_tb.o /home/wu/riscv/ara/hardware/tb/verilator/ara_tb.cpp
g++ -I. -MMD -I/home/wu/riscv/ara/install/verilator/share/verilator/include -I/home/wu/riscv/ara/install/verilator/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=c++11 -Wall -DTOPLEVEL_NAME=ara_tb_verilator -DNR_LANES=4 -I/home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp -I/home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp -I/home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp -std=gnu++14 -Os -c -o dpi_memutil.o /home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp/dpi_memutil.cc
g++ -I. -MMD -I/home/wu/riscv/ara/install/verilator/share/verilator/include -I/home/wu/riscv/ara/install/verilator/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=c++11 -Wall -DTOPLEVEL_NAME=ara_tb_verilator -DNR_LANES=4 -I/home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp -I/home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp -I/home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp -std=gnu++14 -Os -c -o sv_scoped.o /home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp/sv_scoped.cc
g++ -I. -MMD -I/home/wu/riscv/ara/install/verilator/share/verilator/include -I/home/wu/riscv/ara/install/verilator/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=c++11 -Wall -DTOPLEVEL_NAME=ara_tb_verilator -DNR_LANES=4 -I/home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp -I/home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp -I/home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp -std=gnu++14 -Os -c -o verilator_memutil.o /home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp/verilator_memutil.cc
/home/wu/riscv/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp/dpi_memutil.cc:11:10: fatal error: libelf.h: No such file or directory
11 | #include <libelf.h>
| ^~~~~~~~~~
compilation terminated.
make[1]: *** [Vara_tb_verilator.mk:75: dpi_memutil.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make[1]: Leaving directory '/home/wu/riscv/ara/hardware/build/verilator'
make: *** [Makefile:127: build/verilator/Vara_tb_verilator] Error 2

thanks

I see the vrgather test by default is disabled (not even compiling), and a simple try-out of vrgather causes the simulation to error out.

does ara support vrgather already?

Thanks.