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Chi Zhang's Projects

ara icon ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

dlrm icon dlrm

An implementation of a deep learning recommendation model (DLRM)

dramsys icon dramsys

DRAMSys a SystemC TLM-2.0 based DRAM simulator.

mechasvg icon mechasvg

Python application for creating energy profile diagrams as '.svg' files. Extra analysis for catalytic cycle diagrams.

mempool icon mempool

A 256-RISC-V-core system with low-latency access into shared L1 memory.

piperv32n icon piperv32n

A 4 stage pipelined 32-bit RISCV core with only 8 base integer registers

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