Topic: riscv Goto Github

👇 Here are 805 public repositories matching this topic...

andrescv / jupiter
riscv,RISC-V Assembler and Runtime Simulator
User: andrescv
Home Page: https://jupitersim.gitbook.io/
riscv risc-v rv32 simulator riscv-simulator risc assembler runtime-simulator education asm

arcemu / arcemu
riscv,World Of Warcraft 3.3.5a server
Organization: arcemu
warcraft vagrant docker world-of-warcraft worldofwarcraft cpp c-plus-plus cmake docker-compose wow

ariya / fastlz
riscv,Small & portable byte-aligned LZ77 compression
User: ariya
Home Page: https://ariya.github.io/FastLZ
compression lz77 lempel-ziv c fastlz ansi-c c90 c99 amd64 intel

bet4it / udbserver
riscv,Unicorn Emulator Debug Server - Written in Rust, with bindings for C, Go, Java and Python
User: bet4it
debugging emulator reverse-engineering gdb gdbserver bindings rust-ffi aarch64 arm mips

capstone-engine / capstone
riscv,Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.
Organization: capstone-engine
Home Page: http://www.capstone-engine.org
reverse-engineering disassembler security framework arm arm64 x86 sparc powerpc mips

chipsalliance / cores-veer-eh1
riscv,VeeR EH1 core
Organization: chipsalliance
processor risc riscv risc-v fusesoc verilator western-digital open-source-hardware rtl fpga

chipsalliance / rocket-chip
riscv,Rocket Chip Generator
Organization: chipsalliance
scala rocket-chip chip-generator chisel riscv rtl

d0iasm / rvemu
riscv,RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).
User: d0iasm
Home Page: https://rvemu.app/
emulator rust riscv riscv-emulator riscv-simulator

d0iasm / rvemu-for-book
riscv,Reference implementation for the book "Writing a RISC-V Emulator in Rust".
User: d0iasm
Home Page: http://book.rvemu.app/
emulator xv6 rust riscv riscv-emulator

darklife / darkriscv
riscv,opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Organization: darklife
riscv processor-design rv32i rv32e verilog risc-v fpga rtl softcore core

eugene-tarassov / vivado-risc-v
riscv,Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
User: eugene-tarassov
nexys-video risc-v linux xilinx vivado fpga vc707 genesys2 boom rocketchip

eunomia-bpf / eunomia-bpf
riscv,Build, Distribute and Run CO-RE eBPF programs easier with JSON and Webassembly OCI images
Organization: eunomia-bpf
Home Page: https://eunomia.dev
ebpf ebpf-co-re function-as-a-service wasm libbpf linux webassembly oci oci-image oras

f32c / f32c
riscv,A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
Organization: f32c
fpga altera lattice xilinx riscv mips arduino

fwsgonzo / libriscv
riscv,The fastest RISC-V sandbox
User: fwsgonzo
risc-v riscv-emulator userspace cpp emulator riscv binary-translation interpreter cpp20 low-latency

github0null / eide
riscv,An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.
User: github0null
Home Page: https://em-ide.com
c51 stm32 8051 stm8 mcs51 sdcc armcc gcc arm vscode

jameslzhu / riscv-card
riscv,An unofficial assembly reference for RISC-V.
User: jameslzhu
berkeley isa riscv reference asm latex

larsbrinkhoff / lbforth
riscv,Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.
User: larsbrinkhoff
forth compiler interpreter metacompiler pdp11 m68k self-hosted linux arm programming-language

lekkit / rvvm
riscv,The RISC-V Virtual Machine
User: lekkit
risc-v riscv riscv32 riscv-emulator vm virtual-machine emulator emulation emulators c

michaeljclark / rv8
riscv,RISC-V simulator for x86-64
User: michaeljclark
Home Page: https://michaeljclark.github.io/
isa simulator disassembler emulator riscv binary-translation metadata histogram risc macro-op-fusion

mikeroyal / risc-v-guide
riscv,RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
User: mikeroyal
risc-v riscv64 riscv-emulator sbc peripherals sel4 computer-architecture processor-architecture risc-processor platformio

misprit7 / computerraria
riscv,A fully compliant RISC-V computer made inside the game Terraria
User: misprit7
Home Page: https://youtu.be/zXPiqk0-zDY
logic-gates risc-v riscv terraria terraria-mod

nervosnetwork / ckb-vm
riscv,CKB's vm, based on open source RISC-V ISA
Organization: nervosnetwork
Home Page: https://www.nervos.org/
nervos ckb blockchain rust riscv smart-contract

o8vm / octox
riscv,Unix-like OS in Rust inspired by xv6-riscv
User: o8vm
rust xv6-riscv riscv osdev

oaid / tengine
riscv,Tengine is a lite, high performance, modular inference engine for embedded device
Organization: oaid
arm machine-learning artificial-intelligence cnn tensorflow pytorch onnx x86-64 mips cuda

openhwgroup / cv32e40p
riscv,CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Organization: openhwgroup
Home Page: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest
riscv riscv32imfc

oreboot / oreboot
riscv,oreboot is a fork of coreboot, with C removed, written in Rust.
Organization: oreboot
oreboot rust hacktoberfest bootloader firmware linux os riscv

probe-rs / probe-rs
riscv,A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host
Organization: probe-rs
Home Page: https://probe.rs
arm debug rust coresight probe-rs arm-cores daplink debug-probes jlink stlink

pulp-platform / ara
riscv,The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
Organization: pulp-platform
ara riscv rvv rv64gcv asic cpu vector

pulp-platform / pulp-dronet
riscv,A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP
Organization: pulp-platform
autonomous-quadcoptor cnn artificial-intelligence nano-uav end-to-end-learning closed-loop-control deep-learning pulp riscv

rcore-os / rcore
riscv,Rust version of THU uCore OS. Linux compatible.
Organization: rcore-os
rust osdev riscv x86-64 aarch64 mips

riscv-boom / riscv-boom
riscv,SonicBOOM: The Berkeley Out-of-Order Machine
Organization: riscv-boom
riscv boom chisel rtl rocket-chip scala riscv-boom berkeley

riscv-mcu / e203_hbirdv2
riscv,The Ultra-Low Power RISC-V Core
Organization: riscv-mcu
Home Page: https://doc.nucleisys.com/hbirdv2
risc-v riscv fpga hummingbird nuclei soc e203 china verilog low-power

riscv / meta-riscv
riscv,OpenEmbedded/Yocto layer for RISC-V Architecture
Organization: riscv
Home Page: https://riscv.org/
risc-v riscv yocto yocto-layer yocto-meta openembedded openembedded-layer

rustsbi / rustsbi
riscv,RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see https://github.com/rustsbi/prototyper.
Organization: rustsbi
rust rustsbi rust-embedded riscv sbi sbi-specification bare-metal

sergeykhbr / riscv_vhdl
riscv,Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
User: sergeykhbr
Home Page: http://sergeykhbr.github.io/riscv_vhdl/
riscv soc vhdl simulator systemc qt cpu debugger

sipeed / maixpy-v1
riscv,MicroPython for K210 RISC-V, let's play with edge AI easier
Organization: sipeed
Home Page: https://wiki.sipeed.com/maixpy
maixpy k210 aiot micropython edge-ai riscv firmware

spinalhdl / vexriscv
riscv,A FPGA friendly 32 bit RISC-V CPU implementation
Organization: spinalhdl
riscv soc cpu spinalhdl vhdl verilog fpga softcore

splinedrive / kianriscv
riscv,RISC-V Linux SoC, marchID: 0x2b
User: splinedrive
riscv verilog fpga cpu linux bare-metal mmu rv32ima sv32 systemverilog

stnolting / neorv32
riscv,:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
User: stnolting
Home Page: https://neorv32.org
risc-v soft-core vhdl fpga soc microcontroller processor cpu riscv system-on-chip

syntacore / scr1
riscv,SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Organization: syntacore
riscv risc-v rtl verilog rv32i rv32e rv32imc rv32emc ip core

sysprog21 / rv32emu
riscv,Compact and Efficient RISC-V RV32I[MAFC] emulator
Organization: sysprog21
emulator risc-v riscv riscv32 riscv-emulator bare-metal rv32imac riscv-simulator gdbstub remote-debugging

sysprog21 / shecc
riscv,A self-hosting and educational C optimizing compiler
Organization: sysprog21
arm armv7 compiler self-hosting c linux risc-v rv32i rv32im riscv

takahirox / riscv-rust
riscv,RISC-V processor emulator written in Rust+WASM
User: takahirox
Home Page: https://takahirox.github.io/riscv-rust/wasm/web/index.html
rust riscv risc-v emulator cpu processor webassembly wasm

tencent / ncnn
riscv,ncnn is a high-performance neural network inference framework optimized for the mobile platform
Organization: tencent
inference high-preformance simd arm-neon deep-learning artificial-intelligence android ios ncnn vulkan neural-network caffe mxnet pytorch onnx darknet tensorflow mlir keras riscv

thethirdone / rars
riscv,RARS -- RISC-V Assembler and Runtime Simulator
User: thethirdone
mars risc-v riscv assembler simulator ide education

ucb-bar / chipyard
riscv,An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Organization: ucb-bar
Home Page: https://chipyard.readthedocs.io/en/stable/
rocket-chip chip-generator chisel riscv rtl soc peripherals chipyard risc-v boom

ucb-bar / riscv-mini
riscv,Simple RISC-V 3-stage Pipeline in Chisel
Organization: ucb-bar
chisel riscv rtl

unicorn-engine / unicorn
riscv,Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
Organization: unicorn-engine
Home Page: http://www.unicorn-engine.org
emulator framework cpu arm arm64 mips m68k sparc x86 x86-64

wangxuan95 / ustc-rvsoc
riscv,An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
User: wangxuan95
Home Page: https://gitee.com/wangxuan95/USTC-RVSoC
riscv risc-v rv32i soc fpga softcore rtl verilog systemverilog cpu

windelbouwman / ppci
riscv,A compiler for ARM, X86, MSP430, xtensa and more implemented in pure Python
User: windelbouwman
Home Page: https://ppci.readthedocs.io/en/latest/
compiler msp430 xtensa riscv assembler c-preprocessor c-compiler python webassembly arm