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Name: Yuning Li
Type: User
Company: Leibniz Universität Hannover
Name: Yuning Li
Type: User
Company: Leibniz Universität Hannover
Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional periperals.
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
the implementation of the ASAD_DenseNet
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
📖 北京理工大学非官方 LaTeX 模板集合,包含本科、研究生毕业设计模板及更多。🎉 (更多文档请访问 wiki 和 release 中的手册)
Deep Learning Accelerator (Convolution Neural Networks)
Convolutional accelerator kernel, target ASIC & FPGA
使用Verilog实现的CNN模块,可以方便的在FPGA项目中使用
AXI interface modules for Cocotb
Common SystemVerilog components
SystemVerilog modules and classes commonly used for verification
CNN acceleration on virtex-7 FPGA with verilog HDL
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Accelerator
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
4 stage, in-order, compute RISC-V core based on the CV32E40P
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
The Ultra-Low Power RISC-V Core
A Verilog implementation of a CNN accelerator.
POSSUMM - PCA of Sparse, SUper Massive Matrices
ES-203 Computer Organization & Architecture CNN on FPGA board
🍀 Tensorflow implementation of various Attention Mechanisms, MLP, Re-parameter, Convolution, which is helpful to further understand papers.⭐⭐⭐
An Eyeriss Chip (researched by MIT, a CNN accelerator) simulator and New DNN framework "Hive"
Matlab PCA 人脸识别
Hardware implementation of a Fixed Point Recursive Forward and Inverse FFT algorithm
Radix 2 DIT FFT Single Path Delay Feedback
FPGA implementation of Cellular Neural Network (CNN)
An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。
A declarative, efficient, and flexible JavaScript library for building user interfaces.
🖖 Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
An Open Source Machine Learning Framework for Everyone
The Web framework for perfectionists with deadlines.
A PHP framework for web artisans
Bring data to life with SVG, Canvas and HTML. 📊📈🎉
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
Some thing interesting about web. New door for the world.
A server is a program made to process requests and deliver data to clients.
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
Some thing interesting about visualization, use data art
Some thing interesting about game, make everyone happy.
We are working to build community through open source technology. NB: members must have two-factor auth.
Open source projects and samples from Microsoft.
Google ❤️ Open Source for everyone.
Alibaba Open Source for everyone
Data-Driven Documents codes.
China tencent open source team.