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An unofficial assembly reference for RISC-V.

License: Creative Commons Attribution 4.0 International

TeX 100.00%

berkeley isa riscv reference asm latex

riscv-card's Introduction

RISC-V Reference Card

An unofficial reference sheet for RISC-V, the free and libre ISA from Berkeley. (PDF).

What's inside?

The base ISA (RV32I), with opcode values and C-like descriptions
Standard ISA extensions (most but not all yet)
Register aliases and calling conventions
Pseudoinstructions

Other information from the more official reference cards not specific to the ISA, like the stack/heap memory layout, IEEE 754 floating-point layout, and size prefixes, have been omitted.

Why?

In RISC tradition, the assembly reference for MIPS and RISC-V fits onto a single double-sided 'Green Sheet'.

When I took CS 61C at UC Berkeley in 2017, we were the first semester taught using RISC-V, and our reference card scans from our RISC-V textbook were low-quality. I wanted a card I didn't have to squint at, so I typeset it in LaTeX.

The latest Berkeley course reference card is also available.

This little reference has grown well past a double-sided page, but if you still want the original you can print the first and last pages for the asm opcodes and calling convention.

Contributing

This repository is not actively developed, but pull requests are accepted for fixes, new ISA standard extensions, style improvements, or other such changes. Please include a rebuilt PDF binary in your pull request.

Print-friendly format is preferred, when possible: legible font sizes, clean page breaks and full letter page width usage. (A4 support may be a good thing to check.)

Some ideas if you are truly motivated:

Multiple outputs (pdfs) for different domains / ISA extension sets, or for 32 / 64-bit support
Directly parsing the spec, banishing typos forever
Build system to select binary or hex instruction opcodes
Other ISA support? (probably only feasible for RISC ISAs)

Licensing

This work is licensed under the Creative Commons CC-BY-4.0 license. (See LICENSE for the full text.)

In brief, feel free to use this for your own purposes, as long as you credit me, and don't restrict others. (Again, read the license for the specifics.)

This work is adapted from the RISC-V Instruction Set Manual, available at https://riscv.org/specifications/ and licensed under the Creative Commons CC-BY-4.0 license.

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riscv-card's Issues

A lingering asterisk

The text in "Shift Right Arith*" has an asterisk with no apparent purpose.

Misplaced comments in Notes column

@esmil The Notes column, the first two "zero-extends" comments are mis-placed. They should be beside the Logical Shift Right commands, not the Set Less Than instructions. @

sltiu note incorrect? (RV32I Base Integer Instructions)

Is this note correct? I believe the immediate field is sign extended (not zero extended) and then is treated (along with rs1) as an unsigned value for the comparison.

See RISC-V Instruction Set Manual, Volume I: Unprivileged ISA, December 13, 2019. Page 18:

"SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the sign extended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is
similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to
XLEN bits then treated as an unsigned number)."

JALR immediate handling

See pp 15-16 of https://content.riscv.org/wp-content/uploads/2016/06/riscv-spec-v2.1.pdf . JALR adds imm[11:0] (sign-extended) and rs1 to generate new PC.

sltu note incorrect? (RV32I Base Integer Instructions)

Is this note correct? Both source operands are registers. What is being zero-extended? The < comparison is treating both operands as unsigned but nothing is being sign-extended or zero-extended.

Incorrect instruction

The branch greater equal (bge) instruction is with the '≤' sign instead of '≥'

Mnemonic for RV32M mispelled

Two mnemonic in RV23M seem mispelled:

"mulu" should be "mulhu"
"mulsu" should be "mulhsu"

Is there any introduction to RISC-V64 and CSR registers?

Is this project still mataining?

If so, it would be great to have some content about RISC-V64 instructions and CSR registers.

Thanks.

Description of FNMADD and FNMSUB is swapped

Per ISA spec:

FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and
writes the final result to rd. FNMSUB.S computes -(rs1×rs2)+rs3.
FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3,
and writes the final result to rd. FNMADD.S computes -(rs1×rs2)-rs3.
..
The FNMSUB and FNMADD instructions are counterintuitively named, owing to the naming
of the corresponding instructions in MIPS-IV.