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Simple RISC-V 3-stage Pipeline in Chisel

License: Other

Makefile 2.64% Scala 89.47% Shell 1.07% Assembly 0.06% C 0.09% C++ 6.66%

chisel riscv rtl

riscv-mini's Introduction

riscv-mini

Author: Donggyu Kim ([email protected])

riscv-mini is a simple RISC-V 3-stage pipeline written in Chisel. It has been a crucial example in various project developments, including Chisel3, FIRRTL, Strober, simulation and verification methodologies. It implements RV32I of the User-level ISA Version 2.0 and the Machine-level ISA of the Privileged Architecture Version 1.7. Unlike other simple pipelines, it also contains simple instruction and data caches.

Note that a real-world processor is not the goal of riscv-mini. It is developed as an intermediate example before diving into rocket-chip.

Datapath Diagram

Getting Started

$ git clone https://github.com/ucb-bar/riscv-mini.git
$ cd riscv-mini
$ make            # generate firrtl & verilog files in generated-src

The verilog output file can be used for verilator simulation or the ASIC tool flow.

Running Verilator Simulation

First, generate the verilator binary:

$ make verilator

This will generate VTile in the top-level directory.

Now, you can run verilator simulation for a given hex file as follows:

$ ./VTile <hex file> [<vcd file> 2> <log file>]

<vcd file> and the pipe to <log file> are optional. The waveform is dumped to dump.vcd and the execution trace is printed in the screen by default.

The following command runs the whole test hex files in verilator and dumps the traces and the waveforms to the 'outputs' directory:

$ make run-tests

Unit and Integration Tests with `sbt`

riscv-mini provides synthesizable unit & integration tests. Theres are six sets of unit tests(ALUTests, BrCondTests, ImmGenTests, CSRTests, CacheTests, DatapathTests), running user-defined test vectors. To execute them, first launch sbt with make sbt and run:

> testOnly mini.[testname]

There are also six sets of integration tests, running the hex files from riscv-tests. To execute them, also launch sbt and run:

> testOnly mini.[Core|Tile][Simple|ISA|Bmark]Tests

Core only contains the datapath and the control unit, while Tile also contains I$ and D$. Simple only runs rv32ui-p-simple, ISA runs the whole ISA tests, and Bmark runs five benchmarks(median, multiply, qsort, towers, vvadd). Note that all tests in a set run in parallel.

Finally, to run all the tests, just in sbt:

> test

Running Your Own Program on `riscv-mini`

At this point, you may want to implement and exeucte your custom application on riscv-mini. In this case, you need to install RISC-V tools for priv 1.7. This repo provides a script to install the correct version of tools. Run the script as follows:

$ export RISCV=<path to riscv tools for priv 1.7>
$ ./build-riscv-tools

It takes a while to install the toolchain, so please be patient.

This repo also provides a template for your own program in custom-bmark. Add your c or assembly code and edit Makefile. Next, to compile you program, run make in custom-bmark to generate the binary, dump, and the hex files. Finally, run the following command in the base directory:

$ make run-custom-bmark

riscv-mini's People

Contributors

Stargazers

Watchers

Forkers

songmaotian sbhakim hossein1387 jrrk citrus-lemon jtxiao82 felixonmars jianpingzeng mediapastor songjunjian lvcargnini maixianyu younghogong xianjunzhengbackup zhantaocheng liangfu gerent9196 peaksong abulila dreamflyings y-bobo suedongchu jeremykirscht yangwang92 chisuhua 2php ibndias rayjyh liangkangnan ocakgun yonghua719 xiaolongn100 leonardt junweid szu17dmy shi27feng hz0ne loulansuiye xiwenx winfredsu ekiwi noloerino kakiryan catonblack engraff92 paranlee mfkiwl dzwduan luxtonychen yonggeshidai awanik liuyic00 dongdeji yujiang019 x-tinkerer vighneshiyer adwait huangliwood haibaramegumi lzufalcon wataru030-xiaohei sinaden laplacekorea qshan wisherhxl gz tvrctkmytfln wustl-frisc obiwanrohan mola068 lingzichao jinwookjungs maxcamp kaushik-shiva20 emjunaid zewencui 648lsf yummy0929 hq-ankou sandyman acproject jasonyanyusong johnson066 ekerneljoy tousifrahman occupymars2025 seddonshen kuyousou letienhung kuanch emin017 ieda-open-source-core-project kleenelan ftppz haplv clownsw ethanhau amagicman yakkhini priyanshumishra77

riscv-mini's Issues

Proposal to Update Project to Latest Chisel

I'd like to propose the following.

Make the current master branch become the release branch
- Make release be the default branch in this repo
- It will, for now, continue to point to its desired version of chisel3
- This would allow us to work on master, buffering existing users
After the above change master branch
1. Point to current 3.2-SNAPSHOT
2. Fix all code to be compliant and as warning free as possible with Chisel 3.2
3. put all code in main and tests into a mini package
  - This will bring it in line with standard Scala conventions
Change master to depend on chisel-testers2 instead of chisel3
- This would allow us to develop some testers2 style unit tests
  - This would help test out testers2 capabilities
  - Provide alternative examples of unit testing facilities under chisel

Strobe writes broken in TileTester.

The way that strobe writes are implemented in TileTester.scala is broken. As it is now, it creates a Wire 70 bits long and writes junk data to the testing memory. I fixed with the following lines of code:

val blastBytes = nasti.dataBits / 8
val write = (VecInit.tabulate(blastBytes)(byte => (Mux(dut.io.nasti.w.bits.strb(byte), dut.io.nasti.w.bits.data, _mem(addr + off)))(8 * (byte + 1) - 1, 8 * byte))).asUInt

I don't know if this would be the preferred fix, but I just wanted to let you all know.

Running simulation with other programs?

I saw that the provided tests run the existing hex files.
How can I run my own programs on this platform?
I tried to compile and transfer the vvadd program in riscv-tests to hex file,
then replace the vvadd.riscv.hex in src/test/resources.
But the test fails:

CoreTests.scala:61 assert(cycle < maxcycles.U)

Can you provide complete building steps?
Thanks!

NastiArbiter IO forgot wrap in IO

In the nasti.scala file, the IO of the module NastiArbiter miss IO wrap

instruction doesn't appear in spec?

Hello, Kim, I have a question that FENCEI doesn't appear in the riscv-isa-manual, did I miss some thing?

encountered error when performing make"firtool returned a non-zero exit code. Note that this version of Chisel (5.0.0) was published against firtool version 1.40.0."

I download firrtl 2.13_1.4.0.jar and add it into project lib,but the error still occur.

Cannot run program "z3"CreateProcess error=2, system cant find the file specified

I run ALUTests.scala in intelliJIDEA under windows,but encountered this error.
I have installed verilator by cygwin and add environment variable into PATH.

Underlying behavior of each module

Hi,

I've started coding Chisel the past few weeks and I have to work on the risc v mini processor. I am having troubles following which signal is used for what in code. I also do not understand how is the freechips.rocketchip.config suppose to work. So my question is: do you have a report or a commented version of the code that contains the description of the intern signals of each module ?

Thank you

make run-tests errors

Generated Tile.v won't compile

Hi.

I was trying to follow your instructions on README.md to get verilator tests running, before encountering the following error

hob:riscv-mini/ (master) $ make verilator
verilator --cc --exe --assert -Wno-STMTDLY -O3 --trace --top-module Tile -Mdir /home/hob/Programs/test/riscv-mini/generated-src/VTile.csrc -CFLAGS "-std=c++11 -Wall -Wno-unused-variable -include /home/hob/Programs/test/riscv-mini/generated-src/VTile.csrc/VTile.h"  -o /home/hob/Programs/test/riscv-mini/VTile /home/hob/Programs/test/riscv-mini/generated-src/Tile.v /home/hob/Programs/test/riscv-mini/src/main/cc/top.cc /home/hob/Programs/test/riscv-mini/src/main/cc/mm.cc
%Error: /home/hob/Programs/test/riscv-mini/generated-src/Tile.v:3397: syntax error, unexpected INTEGER NUMBER, expecting IDENTIFIER
%Error: Exiting due to 1 error(s)
%Error: Command Failed /usr/bin/verilator_bin --cc --exe --assert -Wno-STMTDLY -O3 --trace --top-module Tile -Mdir /home/hob/Programs/test/riscv-mini/generated-src/VTile.csrc -CFLAGS '-std=c++11 -Wall -Wno-unused-variable -include /home/hob/Programs/test/riscv-mini/generated-src/VTile.csrc/VTile.h' -o /home/hob/Programs/test/riscv-mini/VTile /home/hob/Programs/test/riscv-mini/generated-src/Tile.v /home/hob/Programs/test/riscv-mini/src/main/cc/top.cc /home/hob/Programs/test/riscv-mini/src/main/cc/mm.cc
Makefile:28: recipe for target '/home/hob/Programs/test/riscv-mini/VTile' failed
make: *** [/home/hob/Programs/test/riscv-mini/VTile] Error 10

The sbt tests fail as a result too.

It says that there's a syntax error on the 3397th line of Tile.v, which is

          $fwrite(32'h80000002,"PC: %h, INST: %h, REG[%d] <- %h\n",ew_pc,ew_inst,_T_296,_T_298); // @[Datapath.scala 172:11]

However if I change fwrite to display and delete that 32'h80000002 it compiles without problem.

My setup:

$ git clone https://github.com/ucb-bar/riscv-mini.git 
$ cd riscv-mini
$ make  # it tells me there's 68 feature warnings
$ make verilator

My environment:

Ubuntu 16.04
Verilator 3.874 2015-06-06 rev verilator_3_872-20-g0d43051 (just the one from apt install)
Scala version 2.11.6 (OpenJDK 64-Bit Server VM, Java 1.8.0_171).

Could you tell my if there's anything I's wrong or missed?
Thank you very much.

How do I add a new register under the source code of src, and then use GTKWave to see this register when viewing the waveform?

Is riscv-mini a single-cycle-processor?

By the way,where can I get trainning about chisel develop for AXI, DMA,SRAM ,etc.
Thanks

Problems related to asSint type conversion to verilog file (.sv)

in the version chiselVersion = "5.0.0" chiseltestVersion = "5.0.2" version riscvmini:
the code in datapath

` val load = MuxLookup(ld_type, io.dcache.resp.bits.data.zext)(
    Seq(
      LD_LH -> lshift(15, 0).asSInt,
      LD_LB -> lshift(7, 0).asSInt,
      LD_LHU -> lshift(15, 0).zext,
      LD_LBU -> lshift(7, 0).zext
    )
  )`

the Sint target trans to .sv lead to

'wire [3:0][32:0] _GEN =
    {{{1'h0, _csr_io_out}},
     {{1'h0, ew_reg_pc + 32'h4}},
     {ld_type == 3'h5
        ? {25'h0, lshift[7:0]}
        : ld_type == 3'h4
            ? {17'h0, lshift[15:0]}
            : ld_type == 3'h3
                ? {{25{lshift[7]}}, lshift[7:0]}
                : ld_type == 3'h2
                    ? {{17{lshift[15]}}, lshift[15:0]}
                    : {1'h0, io_dcache_resp_bits_data}},
     {{1'h0, ew_reg_alu}}};'

and the width of regfile should be 32 ,but it is 32 .it predict width of sint to 33 ,with log :
' chisel3.package$ChiselException: Connection between sink (Datapath.load: Wire[UInt<32>]) and source (Datapath.load_?: OpResult[SInt<33>]) failed @: Sink (UInt<32>) and Source (SInt<33>) have different types'

and i find the old riscv-mini verion which has sbt

`ThisBuild` / scalaVersion     := "2.13.7"
ThisBuild / version          := "2.5.0"
ThisBuild / organization     := "edu.berkeley.cs"'

it trans to file v with the same chisel code and the code is :

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [63:0] _RAND_14;
...
  wire [32:0] load = 3'h5 == ld_type ? $signed({{24{_load_T_8[8]}},_load_T_8}) : $signed(_load_T_14); // @[Mux.scala 81:58]
  wire [32:0] _regWrite_T = {1'b0,$signed(ew_reg_alu)}; // @[Datapath.scala 203:18]
  wire [31:0] _regWrite_T_2 = ew_reg_pc + 32'h4; // @[Datapath.scala 204:48]
  wire [32:0] _regWrite_T_3 = {1'b0,$signed(_regWrite_T_2)}; // @[Datapath.scala 204:55]
  wire [32:0] _regWrite_T_4 = {1'b0,$signed(csr_io_out)}; // @[Datapath.scala 204:82]
  wire [32:0] _regWrite_T_6 = 2'h1 == wb_sel ? $signed(load) : $signed(_regWrite_T); // @[Mux.scala 81:58]
  wire [32:0] _regWrite_T_8 = 2'h2 == wb_sel ? $signed(_regWrite_T_3) : $signed(_regWrite_T_6); // @[Mux.scala 81:58]
  wire [32:0] regWrite = 2'h3 == wb_sel ? $signed(_regWrite_T_4) : $signed(_regWrite_T_8); // @[Datapath.scala 205:7]

but i think the width of it is 32 is more suitable for sint .so prehaps how can i get some skill to make it to 32 ?
thank you

Is this core based on zcale ?

Does this code have a bug?

in ALU.scala file:
define below:
val ALU_ADD = 0.U(4.W)
val ALU_SUB = 1.U(4.W)
io.sum := io.A + Mux(io.alu_op(0), -io.B, io.B)
in mux ,if io.alu_op(0) is 0 then alu_op is ALU_ADD then Mux(io.alu_op(0), io.B, -io.B) ?

Is this a BUG in TileTester.scala?

riscv-mini/src/test/scala/mini/TileTester.scala

Line 88 in d3bfaf9

id := dut.io.nasti.aw.bits.id

In my view,aw shall be ar , which stands for read address channel in AXI

How to Generate Tile.fir or Tile.mlir in generated-src after Running `make`?

I'm trying to generate either a Tile.fir or Tile.mlir file in the generated-src directory after running the make command. However, I'm facing an issue.

Here's what I've done so far:

I ran make in the terminal as usual.
Then, I tried changing emitSystemVerilogFile to emitCHIRRTL in the code.
After that, I executed sbt 'runMain mini.Main'.
Despite these steps, I'm not seeing the expected Tile.fir or Tile.mlir files in the generated-src directory. It's quite puzzling for me.

Thanks in advance for any help or guidance you can provide!

Error in make command

I tried to follow the steps as given in the RAEADME. But the 'make' command gives an error as below:

sagar@LAPTOP-LRFVFPQJ:~/riscv-mini$ make
sbt -ivy /home/sagar/riscv-mini/.ivy2 "run /home/sagar/riscv-mini/generated-src"
/bin/sh: 1: sbt: not found
Makefile:17: recipe for target '/home/sagar/riscv-mini/generated-src/Tile.v' failed
make: *** [/home/sagar/riscv-mini/generated-src/Tile.v] Error 127
sagar@LAPTOP-LRFVFPQJ:~/riscv-mini$

I'm not sure why this happened.Do help.

Building priv-1.7 riscv-toolchain fails

Hello.

I made sure everything is set-up. The VTile.v is generated, I also got the .HEX pre-compiled tests working. now I want to create some additional software benchmarks. So I tried to build the priv-1.7 toolchain. The build process fails here:

In file included from /home/[.....]/riscv-mini/riscv-tools-priv1.7/riscv-gnu-toolchain/build/src/newlib-gcc/gcc/cp/except.c:1023:0:
cfns.gperf: In function ‘const char* libc_name_p(const char*, unsigned int)’:
cfns.gperf:101:1: error: ‘const char* libc_name_p(const char*, unsigned int)’ redeclared inline with ‘gnu_inline’ attribute
cfns.gperf:26:14: note: ‘const char* libc_name_p(const char*, unsigned int)’ previously declared here
cfns.gperf: At global scope:
cfns.gperf:26:14: warning: inline function ‘const char* libc_name_p(const char*, unsigned int)’ used but never defined
make[3]: *** [cp/except.o] Error 1
make[2]: *** [all-gcc] Error 2
make[1]: *** [all] Error 2
make: *** [stamps/build-gcc-newlib] Error 2

Is there any other working commit ID of riscv-tools that support priv-1.7 and compiles successfully?

[RFC] Upgrade to User-level ISA v2.2 and Privileged Architecture v1.10

Current riscv-mini implements RV32I of the User-level ISA Version 2.0 and the Machine-level ISA of the Privileged Architecture Version 1.7. This requires the users to build and install RISC-V tools for priv 1.7. If we upgrade the implement to user-level ISA to version 2.2 and privileged architecture to version 1.10, users could download latest pre-built compiler from xpack-dev-tools and generate the executable much easier.

Major User-level Base ISA Changes

Changes from v2.1 to v2.2

Rearranged chapters to put all extensions first in canonical order.
Improvements to the description and commentary.
Modified implicit hinting suggestion on JALR to support more efficient macro-op fusion of
LUI/JALR and AUIPC/JALR pairs.
Clarification of constraints on load-reserved/store-conditional sequences.
A new table of control and status register (CSR) mappings.
Clarified purpose and behavior of high-order bits of fcsr.
Specified behavior of narrower (<FLEN) floating-point values held in wider f registers using
NaN-boxing model.
Defined the exception behavior of FMA(∞, 0, qNaN).

Changes from v2.0 to v2.1

Modification to long instruction encodings >64 bits to avoid moving the rd specifier in very
long instruction formats.
CSR instructions are now described in the base integer format where the counter registers
are introduced, as opposed to only being introduced later in the floating-point section (and
the companion privileged architecture manual).
The SCALL and SBREAK instructions have been renamed to ECALL and EBREAK, re-
spectively. Their encoding and functionality are unchanged.
Clarification of LR/SC allowed successes and required failures, including use of compressed
instructions in the sequence.

Major Privileged Architecture Changes

Changes from v1.9.1 to v1.10

Changes from v1.9 to v1.9.1

Numerous additions and improvements to the commentary sections.
Change configuration string proposal to be use a search process that supports various formats
including Device Tree String and flattened Device Tree.
Made misa optionally writable to support modifying base and supported ISA extensions.
CSR address of misa changed.
Added description of debug mode and debug CSRs.
Added a hardware performance monitoring scheme. Simplified the handling of existing hard-
ware counters, removing privileged versions of the counters and the corresponding delta reg-
isters.
Fixed description of SPIE in presence of user-level interrupts.

Changes from v1.7 to v1.9

(Not yet available.)

For more details, please refer to the documents here.

Please leave your comments.

Failed all formal verification.

I tried to run all the tests with sbt test, but found out 3 tests failed. They are ALUTests, ImmGenTests, and BrCondTests, respectively.
They all have formal verification at the end. Is this because wrong chisel version or I lost some package?

My running environment are listed below:

Operating System: Ubuntu 20.04.5 LTS
Java: openjdk 11.0.16 2022-07-19
Chisel: 3.5.1

Formal verification code in ALUTests.scala:

"AluArea" should "be equivalent to AluSimple" in {
      // since there is no state (registers/memory) in the ALU, a single cycle check is enough to prove equivalence
      verify(new AluEquivalenceCheck(new AluArea(32)), Seq(BoundedCheck(1)))
}

Following is the error message from ALUTests:

[info] ALUTests:
[info] ALUSimple
[info] - should pass
[info] AluArea
[info] - should pass
[info] AluArea
[info] - should be equivalent to AluSimple *** FAILED ***
[info]   java.io.IOException: Cannot run program "z3" (in directory "/home/RISC-V_3-stage_Pipeline"): error=2, No such file or directory
[info]   at java.base/java.lang.ProcessBuilder.start(ProcessBuilder.java:1128)
[info]   at java.base/java.lang.ProcessBuilder.start(ProcessBuilder.java:1071)
[info]   at os.proc.proc$lzycompute$1(ProcessOps.scala:128)
[info]   at os.proc.proc$1(ProcessOps.scala:122)
[info]   at os.proc.spawn(ProcessOps.scala:135)
[info]   at chiseltest.formal.backends.smt.SMTLibSolverContext.<init>(SMTLibSolver.scala:119)
[info]   at chiseltest.formal.backends.smt.Z3SMTLib$.createContext(SMTLibSolver.scala:32)
[info]   at chiseltest.formal.backends.smt.SMTModelChecker.check(SMTModelChecker.scala:32)
[info]   at chiseltest.formal.backends.Maltese$.bmc(Maltese.scala:54)
[info]   at chiseltest.formal.Formal$.executeOp(Formal.scala:82)
[info]   ...
[info]   Cause: java.io.IOException: error=2, No such file or directory
[info]   at java.base/java.lang.ProcessImpl.forkAndExec(Native Method)
[info]   at java.base/java.lang.ProcessImpl.<init>(ProcessImpl.java:340)
[info]   at java.base/java.lang.ProcessImpl.start(ProcessImpl.java:271)
[info]   at java.base/java.lang.ProcessBuilder.start(ProcessBuilder.java:1107)
[info]   at java.base/java.lang.ProcessBuilder.start(ProcessBuilder.java:1071)
[info]   at os.proc.proc$lzycompute$1(ProcessOps.scala:128)
[info]   at os.proc.proc$1(ProcessOps.scala:122)
[info]   at os.proc.spawn(ProcessOps.scala:135)
[info]   at chiseltest.formal.backends.smt.SMTLibSolverContext.<init>(SMTLibSolver.scala:119)
[info]   at chiseltest.formal.backends.smt.Z3SMTLib$.createContext(SMTLibSolver.scala:32)
[info]   ...
[info] Run completed in 3 seconds, 705 milliseconds.
[info] Total number of tests run: 3
[info] Suites: completed 1, aborted 0
[info] Tests: succeeded 2, failed 1, canceled 0, ignored 0, pending 0
[info] *** 1 TEST FAILED ***
[error] Failed tests:
[error]         mini.ALUTests
[error] (Test / testOnly) sbt.TestsFailedException: Tests unsuccessful

Test hexfile creation documentation

There is no documentation on how the test hex files are generated.
There could be a script to generate/update the hex files from the riscv-tests repository.

Add command line argument to verilator to support very wide wires

It appears we need to adjust the verilator command line to pass the --max-num-width argument for verilator versions > 4.016.
See verilator/verilator#2082

Test directory naming simplification introduces collisions

I think the new directory naming convention introduced in #27 is a win, but we need an additional component in the name. Many (all?) of the tests are run in parallel, and the CoreSimpleTests and CoreISATests end up sharing the same directory for the rv32ui-p-simple test, and thus colliding (especially on heavily loaded systems):

[info] CoreSimpleTests:
[info] mini.CoreSimpleTests *** ABORTED ***
[info]   java.io.IOException: Cannot run program "./VCoreTester" (in directory "test_run_dir/CoreTester_rv32ui-p-simple"): error=26, Text file busy

Jenkins testing shows collisions generating the simulation source files:

In file included from VTileTester__ALLcls.cpp:3:0:
VTileTester.cpp:11516:1: error: expected ‘}’ at end of input
 }
 ^
VTileTester.cpp:11516:1: error: expected unqualified-id at end of input
VTileTester.cpp:11516:1: error: expected ‘}’ at end of input
VTileTester.cpp:11516:1: error: expected unqualified-id at end of input

riscv-mini doesn't support print and declare the float data type variable

Hi,

I try to use the test.ld, syscall.c and crt.S from (riscv-tools and checkout to 4635ab67966c763a84f7217bc2c20b65dcabc7ec. Those sources exist in riscv-tests/benchmarks/common/. These two steps follow riscv-mini/build-riscv-tools.sh) for building the custom-bmark.

It would be success for compiling program and execute simulation with no any warning like (TOHOST: XXXX).

The simulation warning will occur during execution the system call (like printf) or floating variable computation. The screenshot shows the warning during the previous two scenarios.

main.c

int add(int a, int b);

int main(int argc, char** argv) {
  int res = add(3, 2);

  // Simple float variable computation
  float a = 1.0;
  for(int i = 0; i < 10; i++) {
    a += 0.5;
  }

  return res == 5 ? 0 : -1;
}

Environment

Ubuntu 16.04
riscv-gnu-toolchain installtion (based on riscv-mini/build-riscv-tools.sh)
- riscv32-unknown-elf-gcc (GCC) 5.3.0
Verilator 3.922 2018-03-17

There is an another question. Could riscv-mini team provide the some source code (riscv-mini/src/test/resources/) and its corresponding crt.S, syscall.c, util.h, linker sciprt (test.ld).

Thanks you very much!!

some problem about the code of test

After cloning , I start with the code of "make compile " and then i run the test of "test". but some of the unit test failed with output:
[info] - should be equivalent to AluSimple *** FAILED *** [info] java.io.IOException: Cannot run program "z3" (in directory "/home/digi/code/scala/test/riscv-mini2"): error=2, 没有那个文件或目录 [info] at java.base/java.lang.ProcessBuilder.start(ProcessBuilder.java:1128) [info] at java.base/java.lang.ProcessBuilder.start(ProcessBuilder.java:1071) [info] at os.proc.proc$lzycompute$1(ProcessOps.scala:128) [info] at os.proc.proc$1(ProcessOps.scala:122) [info] at os.proc.spawn(ProcessOps.scala:135) [info] at chiseltest.formal.backends.smt.SMTLibSolverContext.<init>(SMTLibSolver.scala:212) [info] at chiseltest.formal.backends.smt.Z3SMTLib$.createContext(SMTLibSolver.scala:71) [info] at chiseltest.formal.backends.smt.SMTModelChecker.check(SMTModelChecker.scala:33) [info] at chiseltest.formal.backends.Maltese$.bmc(Maltese.scala:72) [info] at chiseltest.formal.Formal$.executeOp(Formal.scala:82) [info] ... [info] Cause: java.io.IOException: error=2, 没有那个文件或目录 [info] at java.base/java.lang.ProcessImpl.forkAndExec(Native Method) [info] at java.base/java.lang.ProcessImpl.<init>(ProcessImpl.java:340) [info] at java.base/java.lang.ProcessImpl.start(ProcessImpl.java:271) [info] at java.base/java.lang.ProcessBuilder.start(ProcessBuilder.java:1107) [info] at java.base/java.lang.ProcessBuilder.start(ProcessBuilder.java:1071) [info] at os.proc.proc$lzycompute$1(ProcessOps.scala:128) [info] at os.proc.proc$1(ProcessOps.scala:122) [info] at os.proc.spawn(ProcessOps.scala:135) [info] at chiseltest.formal.backends.smt.SMTLibSolverContext.<init>(SMTLibSolver.scala:212) [info] at chiseltest.formal.backends.smt.Z3SMTLib$.createContext(SMTLibSolver.scala:71) [info] ...
So i run run the test of unit individually. and find that the error come from the code :
verify(new AluEquivalenceCheck(new AluArea(32)), Seq(BoundedCheck(1)))
is it because of the lack of some bulid-commend? so how can i solve it and avoid the mistake next time ?

after I use quartus II 9.0 to compile Title.v successfully, but I double click ALUArea::alu module turn on error below attached

after I use quartus II 9.0 to compile Title.v successfully, but I double click ALUArea::alu module turn on error as below:

if alu module have a bug ??

Synchronous read?

Do the memory and regfile have synchronous read operation?