Skills: Verilog / SystemVerilog / Makefile / C
- ๐ญ Iโm currently working on SystemVerilog for Design and Synthesis.
- ๐ฑ Iโm currently learning SystemVerilog for RTL
- ๐ฏ Iโm looking to collaborate on ASIC/FPGA/SOC Design.
- ๐ฌ Ask me about Verilog, SystemVerilog
- ๐ซ How to reach me: [email protected]
- ๐ Pronouns: He/Him