anhducdinh Goto Github PK
Name: Stublid_20th01
Type: User
Bio: RTL/DV Design
Name: Stublid_20th01
Type: User
Bio: RTL/DV Design
100DaysofRTL: basic logic gates, mux, half and full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector with Moore, Edge Detector with Mealy
100 Days of RTL
Implemented AHB2APB Bridge using VERILOG HDL and simulated in Xilinix and intel quartus prime
The AHB to APB Bridge is an AHB slave, providing an interface between the high-speed AHB and the low-power APB. Read and Write transfers on the AHB are converted into equivalent Transfers on the APB
Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
RISC-V compliant Timer IP
APB protocol is being used to develop a dual port RAM (64 X 8) having one input data line and one output data line. This RAM would be act as APB slave which would be driven by a master present in the APB bridge.
Designed for Blueberry Semiconductors as a part of Project Deliverable.
An implementation of AMBA AXI4Lite on an FPGA using verilog
In this project different bus architectures : APB , AHP , AXI that are part of AMBA (Advanced Microcontroller Bus Architecture) are implemented
To design test bench of the APB protocol
APB
The master of APB bus is the bridge between the previous system bus and APB bus. This bridge is also a slave to the previous system bus. So, it has two interfaces, previous bus slave interface and APB master interface. Its functionality is to convert complex transfer of the previous system bus to simpler one of APB bus.
APB verification using UVM
Implementation of UART Controller and GPIO Controller connected to APB bus
Verification IP for Watchdog
EE 287 2012 Fall
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.
学习AXI接口,以及xilinx DDR3 IP使用
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Repository gathering basic modules for CDC purpose
A declarative, efficient, and flexible JavaScript library for building user interfaces.
🖖 Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
An Open Source Machine Learning Framework for Everyone
The Web framework for perfectionists with deadlines.
A PHP framework for web artisans
Bring data to life with SVG, Canvas and HTML. 📊📈🎉
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
Some thing interesting about web. New door for the world.
A server is a program made to process requests and deliver data to clients.
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
Some thing interesting about visualization, use data art
Some thing interesting about game, make everyone happy.
We are working to build community through open source technology. NB: members must have two-factor auth.
Open source projects and samples from Microsoft.
Google ❤️ Open Source for everyone.
Alibaba Open Source for everyone
Data-Driven Documents codes.
China tencent open source team.