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100-days-of-rtl

100daysofrtl

100DaysofRTL: basic logic gates, mux, half and full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector with Moore, Edge Detector with Mealy

100daysofrtl_sys

100 Days of RTL

15daysofuvm

ahb-apb

ahb2apb-bridge-rtl-design-using-verilog-hdl

Implemented AHB2APB Bridge using VERILOG HDL and simulated in Xilinix and intel quartus prime

ahb2apb-protocol-bridge

The AHB to APB Bridge is an AHB slave, providing an interface between the high-speed AHB and the low-power APB. Read and Write transfers on the AHB are converted into equivalent Transfers on the APB

ahb3lite_apb_bridge

Parameterised Asynchronous AHB3-Lite to APB4 Bridge.

ahb3lite_timer

RISC-V compliant Timer IP

amba-apb-codes

APB protocol is being used to develop a dual port RAM (64 X 8) having one input data line and one output data line. This RAM would be act as APB slave which would be driven by a master present in the APB bridge.

amba-apb4-bridge-interface

Designed for Blueberry Semiconductors as a part of Project Deliverable.

amba-axi4-lite

An implementation of AMBA AXI4Lite on an FPGA using verilog

amba-bus-protocol

In this project different bus architectures : APB , AHP , AXI that are part of AMBA (Advanced Microcontroller Bus Architecture) are implemented

amba_apb

To design test bench of the APB protocol

amba_apb_protocol

apb-examples

APB

apb-master-bridge

The master of APB bus is the bridge between the previous system bus and APB bus. This bridge is also a slave to the previous system bus. So, it has two interfaces, previous bus slave interface and APB master interface. Its functionality is to convert complex transfer of the previous system bus to simpler one of APB bus.

apb-protocol

apb-protocol-verification-using-uvm

APB verification using UVM

apb_async_cdc

apb_bus_connected_to_gpio_and_uart

Implementation of UART Controller and GPIO Controller connected to APB bus

apb_uart_gpio_verilog

arm_watchdog

Verification IP for Watchdog

asic

EE 287 2012 Fall

asic-design-roadmap

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.

axi-ddr3

学习AXI接口，以及xilinx DDR3 IP使用

axi_dma

axi_systemverilog

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

books

cdc

Repository gathering basic modules for CDC purpose