snbk001,Sudhee,github

Hi there 👋, I am Sudhee

RTL Design learner

Skills: Verilog / SystemVerilog / Makefile / C

🔭 I’m currently working on SystemVerilog for Design and Synthesis.
🌱 I’m currently learning SystemVerilog for RTL
👯 I’m looking to collaborate on ASIC/FPGA/SOC Design.
💬 Ask me about Verilog, SystemVerilog
📫 How to reach me: [email protected]
😄 Pronouns: He/Him

Sudhee's Projects

100daysofrtl

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore

7t_sram

7T SRAM Design submitted as a final report for Cloud Based Analog IC Design Hackathon conducted by IITH, Synopsis and VSD

lin-protocol

LIN (Local Interconnect Network) bus protocol, a serial communication protocol for automotive applications.

snbk001

Config files for my GitHub profile.

verilog-design-examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier

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