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aaml-f21

Accelerator Architectures for Machine Learning homework NYCU 2021

bigdata

大数据比赛项目库

chisel-tutorial

chisel tutorial exercises and answers

cornellcswiki

Student-run wiki for students interested in computer science at Cornell University

esp-isa-sim

Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project

final-project-of-cpp

a game of majictower

git-blog-demo

github-slideshow

A robot powered training repository :robot:

gitqwerty777.github.io

Used for a site

learn-cs61a-2020

matrixsum

fall13 lab, UCB.

my_chisel_example

my hisel_example

python-100-days

Python - 100天从新手到大师

rainbowpoem_demo

This is test repo

ravenoc

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

scale-sim-v2

Repository to host and maintain scale-sim-v2 code

sp21-aes-rocc-accel

AES RoCC Accelerator

systolic-array-implementation-in-rtl-for-tpu

IC implementation of Systolic Array for TPU

test

tnoc-topology-reconfigurable-noc-generator

TNoC

tptpu-sim

A Toy-Purpose TPU Simulator

useful-academic-links

This repo has some usefull links to websites for topics, please fork add and generate a pull-request to join the party

verilog-code-of-synchronus-fifo-design-with-verilog-test-code

A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. There are many other use of FIFO also. FIFO uses a dual port memory and there will be two pointers to point read and write addresses. Here is a generalized block diagram of FIFO.