When sampled UART signal for 28M Samples @10MHz, the protocol analyser takes more than 2mins to decode the data which is too sluggish in my opinion.

Tried to capture an uart stream with only one channel active.
The signal is full of digital noise even there was nothing to capture.

On Dec 15th 2013 you said:
"Of cause! In fact, sigrok already has the I2S decoder, we just need to integrate it to DSLogic."

This was the main reason for my perk.
Can you please tell when this will happen .
Best Regards

When I try and change the SPI protocol decoder Mode Setting, SSn is Active High, the setting goes back to SSn is Active Low and will not change.

Platform: Windows 7, 32bit.

What should we expect from the trigger position?
The trivial behavior seems not working on Rev 0.2.1

Thanks
Dimitar

As we've previously remove the Makefile.in's from libusb (as these can be autogenerated), the addition of the configure script in commit 8736df1c18e987db7926dfc925d6e490fda565598736df1c18e987db7926dfc925d6e490fda56559 doesn't help.

Instead, we can copy the autogen.sh script from libsigrok4DSLogic, and update the instructions.

The specs say: Threshold for 1.8V to 3.6V: 0.7V(Low) / 1.4V(High)
Threshold for 5V: 1.4V(Low) / 3.6V(High)

I find that the system does not work at all below 2.2 V !

Also how can you guess the max voltage from the begining ?
I think it is necessary to add the possibility to manualy set the thresholds.
Best Regards

I'm using DSLogic to decode DS18B20 1-wire signals
I'm clearly seeing DSLogic is receiving signal, but it does not get decoded.
I've tryed different speed settings - that does not make any difference
http://screenshots.ryotsuke.ru/scr_594677e64886.png

I'm using 0.21 version on Windows 7 x64

It is not fixed again !! see Load and Save configuration #47
Are you doing some tests before closing issues ??

I have loaded this file:
http://hydrabus.com/HydraNFC_spi_ss_tests.dsl
Then I configure the SPI:

• Clock phase is buggy shall be 1 but display the file name ???
• Warning loading old files change some channels !! (see the picture for the fix)
• Then I save it as Session (File->Session->Store) to file HydraNFC_spi_ss_tests.dsc
  And the file is saved with 0bytes so it does not work.
• Then I save it as "DSView Data" (File -> Save...) to a new file HydraNFC_spi_ss_tests_.dsl
  If you reload HydraNFC_spi_ss_tests_.dsl it is ok

Conclusion:

• Load/Store for "Session" is broken even with latest release
• Clock phase is buggy shall be 1 but display the file name ??? (even if it choose it as 1)
• Warning loading old files change some channels !! (some channels are hidden in fact => channel 0 & 15 why ??)

You have all files to reproduce this problem.

Hi,

On my Fedora system I had the following problem:

[rsharpe@localhost DSLogic-gui]$ cmake .
-- checking for modules 'libsigrok4DSLogic>=0.2.0;libusb-1.0>=1.0.16'
-- package 'libsigrok4DSLogic>=0.2.0' not found
CMake Error at /usr/share/cmake/Modules/FindPkgConfig.cmake:279 (message):
A required package was not found
Call Stack (most recent call first):
/usr/share/cmake/Modules/FindPkgConfig.cmake:333 (_pkg_check_modules_internal)
CMakeLists.txt:62 (pkg_check_modules)
I have built and installed libsigrok4DSLogic and the pkg definition file is in the same location as libusb.

When I made the following change to DSLogic-gui/CMakeLists.txt, it built:

commit 7e81630
Author: Richard Sharpe [email protected]
Date: Mon Jul 7 20:22:19 2014 -0700

Make DSLogic-gui more portable.

Signed-off-by: Richard Sharpe <[email protected]>

diff --git a/DSLogic-gui/CMakeLists.txt b/DSLogic-gui/CMakeLists.txt
index 539ab0d..f2e563d 100644
--- a/DSLogic-gui/CMakeLists.txt
+++ b/DSLogic-gui/CMakeLists.txt
@@ -52,8 +52,8 @@ endif()
#------------------------------------------------------------------------------

list(APPEND PKGDEPS

•   libsigrok4DSLogic>=0.2.0
  

•   libusb-1.0>=1.0.16
  

•   "libsigrok4DSLogic >= 0.2.0"
  

•   "libusb-1.0 >= 1.0.16"
  

  )

  set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} "${CMAKE_CURRENT_SOURCE_DIR}/cmake_m

It would be easier to read and support the code if it used common formatting standards.

There are several tools that help to maintain formatting and one of them is clang-format. Here is an example how to use it:

find . \( -name \*.cpp -or -name \*.h \) -exec clang-format -i -style='{BasedOnStyle: llvm, ColumnLimit: 100}' '{}' \;

It is possible to create formatting that your prefer and save to .clang-format file.

./configure is right :

checking for strstr... no
checking for strtol... no
checking for strtoul... no
checking for strtoull... no
checking that generated files are newer than configure... done
configure: creating ./config.status
config.status: creating Makefile
config.status: creating version.h
config.status: creating hardware/Makefile
config.status: creating hardware/demo/Makefile
config.status: creating hardware/common/Makefile
config.status: creating hardware/DSL/Makefile
config.status: creating input/Makefile
config.status: creating output/Makefile
config.status: creating libsigrok4DSL.pc
config.status: creating tests/Makefile
config.status: creating config.h
config.status: config.h is unchanged
config.status: executing depfiles commands
config.status: executing libtool commands

libsigrok configuration summary:

  - Package version (major.minor.micro):    0.2.0
  - Library version (current:revision:age): 1:2:0
  - Prefix: /usr/local
  - Building on: i686-pc-linux-gnu
  - Building for: i686-pc-linux-gnu

Detected libraries:

  - glib-2.0 >= 2.32.0: yes (2.40.2)
  - libzip >= 0.10: yes (0.10.1)
  - libserialport >= 0.1.0: no
  - libusb-1.0 >= 1.0.9: no
  - libftdi >= 0.16: no
  - libudev >= 151: no
  - alsa >= 1.0: no
  - check >= 0.9.4: no

Enabled hardware drivers:

  - demo............................ yes
  - DreamSourceLab.................. yes

but when I make, the error comes:

make  all-recursive
Making all in hardware
Making all in demo
  CC       libsigrok4DSL_hw_demo_la-demo.lo
In file included from demo.c:32:0:
../../libsigrok.h:27:18: fatal error: glib.h: No such file or directory
 #include <glib.h>
                  ^
compilation terminated.
make[3]: *** [libsigrok4DSL_hw_demo_la-demo.lo] Error 1
make[2]: *** [all-recursive] Error 1
make[1]: *** [all-recursive] Error 1
make: *** [all] Error 2

And I am sure I installed glib :

 sudo apt-get install glib2.0-dev
正在读取软件包列表... 完成
正在分析软件包的依赖关系树       
正在读取状态信息... 完成       
Note, selecting 'libglib2.0-dev' for regex 'glib2.0-dev'
libglib2.0-dev is already the newest version.
libglib2.0-dev 被设置为手动安装。
升级了 0 个软件包，新安装了 0 个软件包，要卸载 0 个软件包，有 490 个软件包未被升级。

Here with I have attached dsl files, which holds the sampling of 50Mhz SPI CLK signal with setting of 16M samples @100MHz, 200MHz and 400MHz, its quite interesting to know that each file measures different SPI clock rate but at least @200mhz works fine but even then it varies in duty cycle from 50% to 75%, its weird behaviour.

I feel the hardware is stable enough till 25MHz signal beyond that its not promising, if you have different opinion, kindly share.

For the sake of attachment I have renamed the file to png, kindly save and rename it to .dsl

Is it a firmware issue or software issue?

Would it be possible to show the captured data when user presses stop?

http://sigrok.org/wiki/Fx2lafw

Continuous sampling seem to be common quiestion from new DSLogic users.

Sigrok has support for it in form of http://sigrok.org/wiki/Fx2lafw

It would be quite easy to implement if we had VHDL or Verilog source for FPGA image and code for FX. (BTW, which HDL is used?). Even without it and with only pdf schema at
http://www.dreamsourcelab.com/download/Schematic_of_DSLogic_core_board_v1_0.pdf

I think it should be doable. Not that I know how to do it, but I have read through source of fx2lafw, and my main reason for getting this board was FX2 with FPGA but oscilloscope extension got me into side tracked and now I don't have development board any more :-)

Looking at schema, there seems to be four pins (two differential pairs with VCC and GND in between, which might be also used (with... 3.3V limits? 1.8V ? I still have to read through Xilinx FPGA manual...) but they are not diode protected, so normal pins are much better choice.

I don't have time to start working on this any time soon, but would love to have some useful comments about this topic from people with more FPGA experience. When we can expect more documentation and all sources? (FX2, aything for AVR)

I would also love to see more code commits, even non-working versions for which we can submit patches.

When using the windows version on w8.1, the checkboxes in the application are not showing the checked status.
The checkboxes are working as expected but there is no visual feedback what is confusing.

I have hooked 1KHz signal to two dslogic inputs.
If all 16 channels enabled measurements seems to be OK
if less channel enabled for example 4 channels the measurements appears wrong.
At the time the signal should be 1 it is shown as 50MHz (this is at 100Mhz sampling rate) osculations. I guess it is something with the digital filter fixing the probe response or some other FPGA issue.

Dimitar

When adding a stacked decoder and clicking OK, the decoder is not added to the protocol listing and no decode execution takes place, essentially the behavior expected when clicking Cancel. If however, when adding a stacked decoder and clicking Cancel, a decoder is added to the Protocol listing, but only the initial decoder or 1st in the stack is executed.

Please add ability to continuously stream sampling data to hdd so longer period of non-repeated data stream can be analysed.

When I open any dropdown menu osx version of v0.4, the menu items are not readable as they are alligned to right and the menu is not wide enough to show the item in full length.

The sigrok guys would be happy if you would port your changes on libsigrok back to upstream. AFAIK you forked it quite a while ago. Get your changes upstream would be great for users using sigrok and all the existing tools around it with the DSlogic hardware and you wouldn't have to ship a forked source tree and merge upstream changes to it, but could depend on the plain upstream version with all the benefits you get from the sigrok community. Users building your stuff from source (like I did yesterday) could just use the libsigrok from their distribution, which would make using DSlogic even easier. :-)

Hi DreamSourceLab,

I have hooked both ch0 and ch1 to a single 1kHz rectangle signal set sampling to 100Mhz.
In the version 0.2.0 the relative jitter between the two shown signals was normally distributed I think.
Now with Rev 0.2.1 I see edges of the two signal coincide most of the time (so improvements in respect to 0.2 it seems) but from time to time I see 4 samples offset.
Have you changed something related in the FPGA?
If yes keep in mind that amplitude and phase filters the best is to be configurable and optional if possible.

Dimitar

Hello,

I have tried the preliminary 0.4 software

1. It looks better and more solid than 0.3
2. I tried to search for a rising and falling edge in a pattern but search seems doesn't work.
   I think it was working fine in 0.3
3. I still get some high frequency ringing at the edges with new probe and the 1 sample filter set. What does this feature actually do?
4. I got a crash after I selected DAQ, OSC and then back to LA. I don't have oscilloscope extension.

I will be very curious if someone tested the decoders in v0.4?

When we will see dslogic integrated/merged in sigrok. It doesn't make much sense to me to develop dslogic in parallel not fully gain from common efforts.

Thanks.
Dimitar

Trying to get my dslogic pro working and tried the latest master branch but fails to compile with errors as seen in the gist

https://gist.github.com/deepfryed/93260e96427e58a6dd26

Fails with

Building CXX object CMakeFiles/DSView.dir/pv/mainwindow.cpp.o
/home/jerome/GIT/DSLogic/DSView/pv/mainwindow.cpp: In member function ‘bool pv::MainWindow::store_session(QString)’:
/home/jerome/GIT/DSLogic/DSView/pv/mainwindow.cpp:742:77: error: conversion from ‘uint64_t {aka long unsigned int}’ to ‘const QVariant’ is ambiguous
             s_obj["vdiv"] = QJsonValue::fromVariant(dsoSig->get_vDialValue());

Then fails with:

Building CXX object CMakeFiles/DSView.dir/pv/data/decode/annotation.cpp.o
/home/jerome/GIT/DSLogic/DSView/pv/data/decode/annotation.cpp: In constructor ‘pv::data::decode::Annotation::Annotation(const srd_proto_data*)’:
/home/jerome/GIT/DSLogic/DSView/pv/data/decode/annotation.cpp:43:17: error: ‘const struct srd_proto_data_annotation’ has no member named ‘ann_class’
  _format = pda->ann_class;
                 ^
CMakeFiles/DSView.dir/build.make:1695: recipe for target 'CMakeFiles/DSView.dir/pv/data/decode/annotation.cpp.o' failed

Currently the tarball contains no version number. It's usual routine to put one in there to extract tarballs of different release versions into the same folder, so I could have dslogic-0.2 side by side to dslogic-0.3 and so on and have some kind of archive. At the moment you distribute each version as DSLogic.tar.gz and I can not compare them, unless I do the naming myself based on what I download.

I would like to see the following while capturing data:

Pretrigger
Waiting for trigger
PostTrigger

Hello,

I am not sure if I am the only one observing this but in 0.21 all the check boxes and radio buttons can not be selected. They seems to work (get selected) but are not marked if I click on them
I am on Windows 7 64bit.
Anyone having the same?

Dimitar

After cloning the repository and building the libraries and application, its not possible to run the dslogic as non-root user:
sr: ezusb: failed to open device: LIBUSB_ERROR_ACCESS.

Currently the Logic Analyzer app allows to capture digital signal only.

Sometimes it is very useful to capture and compare both digital signal (e.g. I2C) and analog signal (e.g. speaker output) at the same screen. Saleae software allows it. It would be great if DSView was able to do the same.

On Fedora 20 pkg-config apparently only looks for in the following dirs:

> pkg-config --variable pc_path pkg-config
/usr/lib64/pkgconfig:/usr/share/pkgconfig

libsigrok4DSLogic however puts its *.pc files in /usr/local/lib/pkgconfig therefore cmake in DSLogic-gui cannot find them.
For a quick fix you can set the PKG_CONFIG_PATH environment variable to /usr/local/lib/pkgconfig:

export PKG_CONFIG_PATH=/usr/local/lib/pkgconfig

There's one tag in git history at the moment: v1.0. However published v0.2 and v0.21 on your website last, which are not tagged in Git.

I would like option like:

1. 32Msamples for 8 channels.
2. 64Msamples for 4 channels (especially @400Mhz).
3. RLE with timeout limit (in ms/second).

Load and Save configuration including decoder used, channel name and all settings.
As today DSLogic is not usable for multiple protocol tests as we cannot load/save configuration and we shall always reconfigure all from scratch.

There was some error when compiling in pv/mainwindow.cpp wrote the following patch:

diff --git a/DSView/pv/mainwindow.cpp b/DSView/pv/mainwindow.cpp
--- mainwindow.cpp  2015-07-24 19:00:36.621046681 -0300
+++ mainwindow.cpp  2015-07-24 19:01:13.749582511 -0300
@@ -739,8 +739,8 @@
         s_obj["strigger"] = s->get_trig();
         boost::shared_ptr<view::DsoSignal> dsoSig;
         if (dsoSig = dynamic_pointer_cast<view::DsoSignal>(s)) {
-            s_obj["vdiv"] = QJsonValue::fromVariant(dsoSig->get_vDialValue());
-            s_obj["vfactor"] = QJsonValue::fromVariant(dsoSig->get_factor());
+            s_obj["vdiv"] = QString("%1").arg(dsoSig->get_vDialValue());
+            s_obj["vfactor"] = QString("%1").arg(dsoSig->get_factor());
             s_obj["coupling"] = dsoSig->get_acCoupling();
             s_obj["trigValue"] = dsoSig->get_trigRate();
             s_obj["zeroPos"] = dsoSig->get_zeroRate();

There are some compiled/built/log files in the git repo.

There should be removed (and git-ignored), e.g.:

DSLogic-gui/CMakeFiles/CMakeCCompiler.cmake
DSLogic-gui/CMakeFiles/CMakeCXXCompiler.cmake
DSLogic-gui/CMakeFiles/CMakeDetermineCompilerABI_C.bin
DSLogic-gui/CMakeFiles/CMakeDetermineCompilerABI_CXX.bin
DSLogic-gui/CMakeFiles/CMakeDirectoryInformation.cmake
DSLogic-gui/CMakeFiles/CMakeError.log
DSLogic-gui/CMakeFiles/CMakeOutput.log
DSLogic-gui/CMakeFiles/CMakeRuleHashes.txt
DSLogic-gui/CMakeFiles/CMakeSystem.cmake
DSLogic-gui/CMakeFiles/CompilerIdC/CMakeCCompilerId.c
DSLogic-gui/CMakeFiles/CompilerIdC/a.out
DSLogic-gui/CMakeFiles/CompilerIdCXX/CMakeCXXCompilerId.cpp
DSLogic-gui/CMakeFiles/CompilerIdCXX/a.out
DSLogic-gui/CMakeFiles/DSLogic.dir/CXX.includecache
DSLogic-gui/CMakeFiles/DSLogic.dir/DependInfo.cmake
DSLogic-gui/CMakeFiles/DSLogic.dir/build.make
DSLogic-gui/CMakeFiles/DSLogic.dir/cmake_clean.cmake
DSLogic-gui/CMakeFiles/DSLogic.dir/depend.internal
DSLogic-gui/CMakeFiles/DSLogic.dir/depend.make
DSLogic-gui/CMakeFiles/DSLogic.dir/flags.make
DSLogic-gui/CMakeFiles/DSLogic.dir/progress.make
DSLogic-gui/CMakeFiles/Makefile.cmake
DSLogic-gui/CMakeFiles/Makefile2
DSLogic-gui/CMakeFiles/TargetDirectories.txt
DSLogic-gui/CPackConfig.cmake
DSLogic-gui/CPackSourceConfig.cmake
DSLogic-gui/cmake_install.cmake
DSLogic-gui/config.h
libsigrok4DSLogic/Makefile.in
libsigrok4DSLogic/aclocal.m4
libsigrok4DSLogic/autom4te.cache/output.0
libsigrok4DSLogic/autom4te.cache/output.1
libsigrok4DSLogic/autom4te.cache/requests
libsigrok4DSLogic/autom4te.cache/traces.0
libsigrok4DSLogic/autom4te.cache/traces.1
libsigrok4DSLogic/config.h
libsigrok4DSLogic/configure
libsigrok4DSLogic/hardware/DSLogic/Makefile.in
libsigrok4DSLogic/hardware/Makefile.in
libsigrok4DSLogic/hardware/common/Makefile.in
libsigrok4DSLogic/hardware/demo/Makefile.in
libsigrok4DSLogic/input/Makefile.in
libsigrok4DSLogic/output/Makefile.in
libsigrok4DSLogic/output/text/Makefile.in
libsigrok4DSLogic/tests/Makefile.in
libusbx-1.0.18/configure

In DS logic software, sampling shall be made available in the options of ms and sec for the convenience instead of samples in mere numbers so it easy for the user to select what he wants rather than back calculating samples to sec or ms or us.

This similar option is available in saleae logic software.

I don't pretend to know how to code, but I script, and can piece meal other people's work quite handily. :) Know enough about python to edit, and create some hello worlds n such.

So.. Looking at the protocol decoders in sigrok, that are written in python.... Then looking at the Qt based gui stuff from pulseview....

I would like to help to port over some decoders from sigrok.. In particular CAN... What is best way to assist you guys with doing that?

Thanks,
-Kyle

Hi all,

I see issues in Rev 0.2.1 which may be something I am not doing right.
Are you having issues with the following:

• Value of the markers on the plot is always decimal.
• What is floating measurement? Can not be selected
• In the measurement window the "Sample value" is #### for all markers.
  "Value Radix" doesn't do anything it seems.

Thanks
Dimitar

Hi, I get this error when trying to capture 4k samples at 100 MHz on Ubuntu. Any idea what's going wrong?

terminal output:

(process:25504): GConf-WARNING **: Client failed to connect to the D-BUS daemon:
Failed to connect to socket /tmp/dbus-J242kZt6Kt: Connection refused
sr: Sanity-checking all drivers.
sr: Sanity-checking all input modules.
sr: Sanity-checking all output modules.
sr: hwdriver: Initializing driver 'demo'.
sr: hwdriver: Initializing driver 'DSLogic'.
sr: hwdriver: Scan of 'demo' found 1 devices.
sr: Found an DSLogic device.
sr: hwdriver: Scan of 'DSLogic' found 1 devices.
DSLogic attaced!

sr: Firmware upload was not needed.
sr: Opened device 0 on 1.43, interface 0, firmware 1.0.
sr: Detected REVID=1, it's a Cypress CY7C68013A (FX2LP).
sr: Configure FPGA using /usr/local/bin/res/DSLogic.bin
sr: Configure 340604 bytes
sr: FPGA configure done
Starting a hotplug thread...

sr: session: sr_session_stop: session was NULL
sr: session: Starting...
sr: Stop Previous DSLogic acquisition!
sr: FPGA setting done. trigger_mode = 0; trigger_stages = 0; trigger_mask0 = 65535; trigger_value0 = 0; trigger_edge0 = 0
sr: GPIF delay = 0, clocksource = 30MHz.
sr: DSLogic Hardware: Starting acquisition.
sr: DSLogic Hardware: Sending SR_DF_HEADER packet.
sr: session: bus: Received SR_DF_HEADER packet.
sr: session: Running...
sr: receive trigger pos handle...
sr: receive_trigger_pos(): status 0; timeout 0; received 512 bytes.
sr: session: bus: Received SR_DF_TRIGGER packet.
sr: Failed to submit transfer: LIBUSB_ERROR_IO.
sr: receive_trigger_pos: could not start data transfer(-1)

dmesg output:

[1167502.296094] usb 1-6.4: new high-speed USB device number 42 using ehci-pci
[1167502.404356] usb 1-6.4: New USB device found, idVendor=2a0e, idProduct=0001
[1167502.404361] usb 1-6.4: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[1167551.224612] DSLogic[24691]: segfault at 14 ip 0000000000522b0d sp 00007fff390da1c0 error 4 in DSLogic[400000+18f000]
[1167555.584846] usb 1-6.4: USB disconnect, device number 42
[1167557.080110] usb 1-6.4: new high-speed USB device number 43 using ehci-pci
[1167557.188727] usb 1-6.4: New USB device found, idVendor=2a0e, idProduct=0001
[1167557.188732] usb 1-6.4: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[1167557.188735] usb 1-6.4: Product: DSLogic
[1167557.188738] usb 1-6.4: Manufacturer: DreamSourceLab

When I disable all channels and enable only channels 1 and 2 to capture the data and do the acquisition, the same data is displayed in channels 9 and 10 after enabling all 16 channels

Looks like it is something to do with the snapshots deque but haven't tracked it further down than that yet.
#0 0x00007ffff58440ed in __cxa_throw ()

from /usr/lib/x86_64-linux-gnu/libstdc++.so.6
#1 0x00007ffff589df71 in std::__throw_out_of_range_fmt(char const*, ...) ()

from /usr/lib/x86_64-linux-gnu/libstdc++.so.6
#2 0x000000000045bab2 in _M_range_check (__n=0, this=)

at /usr/include/c++/4.9/bits/stl_deque.h:1273

#3 at (__n=0, this=) at /usr/include/c++/4.9/bits/stl_deque.h:1294
#4 pv::SigSession::del_group (this=0x7fffffffd9a8)

at /home/alw/projects/DSLogic/DSView/pv/sigsession.cpp:647

Reproduce:

1. Create a group
2. Delete group immediately without taking any samples

Doesn't seem to matter if the group is the last one/only one or not. However, it does appear to only occur when no samples have been taken.

So this works:

1. Create a group
2. Press "Run" to get samples
3. Delete group

Windows version 0.21 kicks back to demo mode after a few captures. Also notice that when software kicks to demo mode, the dslogic board is no longer in the device drop down list. Restarting application provides a "temporary" workaround.

Hi, when building DSLogic-gui, I needed to install some packages before cmake . would complete successfully:

apt-get install libboost-system-dev libboost-thread-dev libqt4-dev

Might be nice to add that to the INSTALL file.

I have just installed latest DSView from
http://www.dreamsourcelab.com/download/DSView(Beta)_v0.931_setup.exe

1. I load an old file trf7970a_nfm_spi_new_fpga_bitstream_ok.dsl all is ok.
   See file http://hydrabus.com/trf7970a_nfm_spi_new_fpga_bitstream_ok.dsl
2. I save it to a new file trf7970a_nfm_spi_new_ok.dsl all is ok.
   See file http://hydrabus.com/trf7970a_nfm_spi_new_ok.dsl
3. Now if i try to open trf7970a_nfm_spi_new_ok.dsl I obtain error

After inspection (extracting the content of *.dsl files with bin/text compare) it seems only header is corrupted in new file trf7970a_nfm_spi_new_ok.dsl => samplerate = 100 MHz is missing and driver = DSLogic is replaced by driver = virtual-session
data are both identical.

I'd recommend to contact the sigrok devs and try to make DSLogic compatible with vanilla sigrok.

Advantages:

• Being mentioned on http://sigrok.org/wiki/Supported_hardware will lead to more sales of your device
• Users can choose between DSLogic and vanilla Sigrok (=access to sigrok decoders/tools)
• If you merge your changes back to upstream (#5), you may even consider concentrating on the hardware/FPGA development side and leave the main software development to sigrok

The easiest way to achieve sigrok support is probably to contact the sigrok devs at https://lists.sourceforge.net/lists/listinfo/sigrok-devel (Mailing list) or irc://chat.freenode.net/sigrok (IRC) and donate them a free device to play with.

I have an SMT32F103 processor (Spark Core) running a simple program:

pinHI(signalPIN);
pinLO(signalPIN);
pinHI(clkPIN);
pinLO(clkPIN);
pinHI(signalPIN);
pinLO(signalPIN);

At 100Mhz sampling with only 2 channels enabled, the output seems ok though the timing of the pulse edges are off.

At 200MHz sampling with only 2 channels enabled, the first pulse look correct but the second (single) pulse has noise following it.

At 400MHz sampling with only 2 channels enabled, the pulses are smothered by noise on both channels.

The ./configure scripts of libsigrok4DSLogic and libusbx lack the executable flag. Please don't change file permissions before packing the tarball.

Linux distribution uses /usr/bin/res to store firmware files.

Per unix filesystem spec bin directory should be used for binaries only. The data files should be stored in /usr/share. Currently I hardcode like this anatol@34fc17c but it makes more sense to use QStandardPaths::standardLocations(QStandardPaths::AppDataLocation).

Hey, just unpacked my shiny new DSLogic (looks great!) and compiled the software. The GUI freezes though when I run DSlogic and press the aquire (play) button. This is on 64-bit Ubuntu 12.04.4. You can get debs of my binaries (made with checkinstall) here: https://seacloud.cc/f/ad1149d592/

Here is what is printed to terminal:

sr: Sanity-checking all drivers.
sr: Sanity-checking all input modules.
sr: Sanity-checking all output modules.
sr: hwdriver: Initializing driver 'demo'.
sr: hwdriver: Initializing driver 'DSLogic'.
sr: hwdriver: Scan of 'demo' found 1 devices.
sr: Found an DSLogic device.
sr: hwdriver: Scan of 'DSLogic' found 1 devices.
DSLogic attaced!

sr: Firmware upload was not needed.
sr: Opened device 0 on 2.34, interface 0, firmware 1.0.
sr: Detected REVID=1, it's a Cypress CY7C68013A (FX2LP).
sr: Configure FPGA using /usr/local/bin/res/DSLogic.bin
sr: Configure 340604 bytes
sr: FPGA configure done
Starting a hotplug thread...

sr: session: sr_session_stop: session was NULL
sr: session: Starting...
sr: Stop Previous DSLogic acquisition!
sr: FPGA setting done. trigger_mode = 0; trigger_stages = 0; trigger_mask0 = 65535; trigger_value0 = 0; trigger_edge0 = 0
sr: GPIF delay = 0, clocksource = 30MHz.
sr: DSLogic Hardware: Starting acquisition.
sr: DSLogic Hardware: Sending SR_DF_HEADER packet.
sr: session: bus: Received SR_DF_HEADER packet.
sr: session: Running...
sr: receive trigger pos handle...
sr: receive_trigger_pos(): status 0; timeout 0; received 512 bytes.
sr: session: bus: Received SR_DF_TRIGGER packet.
sr: Failed to submit transfer: LIBUSB_ERROR_IO.
sr: receive_trigger_pos: could not start data transfer(-1)
sr: session: Stopping.