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lansen0815's Projects

canopen-stm32f1 icon canopen-stm32f1

基于CANfestival的CANopen协议在STM32F1系列单片机上的实现

dsview icon dsview

An open source multi-function instrument for everyone

opener icon opener

OpENer is an EtherNet/IP stack for I/O adapter devices. It supports multiple I/O and explicit connections and includes objects and services for making EtherNet/IP-compliant products as defined in the ODVA specification.

profinet icon profinet

Minimal Profinet implementation in Python

pyverilog icon pyverilog

Python-based Verilog Parser (currently Netlist only)

vdent icon vdent

Verilog Indenter. Simple indent program for Verilog source code. Trims end of line white space and indents lines based on nested depth of code blocks.

verilog icon verilog

Repository for basic (and not so basic) Verilog blocks with high re-use potential.

verilog-arbiter icon verilog-arbiter

A look ahead, round-robing parametrized arbiter written in Verilog.

verilog-automatic icon verilog-automatic

Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3

veriloggen icon veriloggen

Veriloggen: A library for constructing a Verilog HDL source code in Python

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