Comments (4)
It's odd... Why don't you try a newer version of verilator? Mine is Verilator 3.920 2018-02-01 rev verilator_3_918-16-g13d11b0
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hi, I have a some question about this.
After generate the VTile, I use make run-tests,it shows
and when i use ./VTile median.riscv.hex,it shows that
i don't know what is the problem about this.
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@donggyukim
After upgrading to Verilator 3.920, everything worked without any problem.
Thanks!
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hi, I have a some question about this.
After generate the VTile, I use make run-tests,it shows
and when i use ./VTile median.riscv.hex,it shows that
i don't know what is the problem about this.
Hi, @hfming225 , I have meet the same problem, do you figure out it?
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Related Issues (20)
- Proposal to Update Project to Latest Chisel HOT 4
- Underlying behavior of each module
- [RFC] Upgrade to User-level ISA v2.2 and Privileged Architecture v1.10 HOT 2
- Add command line argument to verilator to support very wide wires
- Test directory naming simplification introduces collisions HOT 1
- How do I add a new register under the source code of src, and then use GTKWave to see this register when viewing the waveform? HOT 1
- Is this core based on zcale ?
- make run-tests errors
- Synchronous read? HOT 1
- Is this a BUG in TileTester.scala? HOT 3
- Test hexfile creation documentation HOT 1
- Failed all formal verification. HOT 2
- Strobe writes broken in TileTester.
- NastiArbiter IO forgot wrap in IO
- How to Generate Tile.fir or Tile.mlir in generated-src after Running `make`? HOT 1
- Cannot run program "z3"CreateProcess error=2, system cant find the file specified HOT 1
- encountered error when performing make"firtool returned a non-zero exit code. Note that this version of Chisel (5.0.0) was published against firtool version 1.40.0." HOT 3
- Is riscv-mini a single-cycle-processor? HOT 1
- some problem about the code of test HOT 2
- Problems related to asSint type conversion to verilog file (.sv) HOT 1
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