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4-way-set-associative-cache-verilog

Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy

arm-legv8

Verilog Implementation of an ARM LEGv8 CPU

arm7

Implemetation of pipelined ARM7TDMI processor in Verilog

arquicoursecpuverilog

An ARMv7 core design using logic works and implemented using icarus verilog.

cacti-m3d

CACTI-M3D / Monolithic 3D Cache Modeling/Simulation Tool

cacti3dd-for-viamodeling

Via modeling

chaidnn

HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

clean-code

Clean Code 스터디의 결과물 정리를 위해 만든 저장소입니다.

coiner

Automatic Cryptocurrency Trading System by using Bithumb API

computerarchitecture

Works of all the labs of Computer Architecture. Contains single-cycle, and pipelined ARM architecture verilog code.

deep-learning-processor-list

A list of ICs and IPs for AI, Machine Learning and Deep Learning.

deepbench

Benchmarking Deep Learning operations on different hardware

digital-flow

This is a tutorial on standard digital design flow

dnn_neurosim_v1.0

ece5745-tut7-pymtl-cl

ECE 5745 Tutorial 5: PyMTL Cycle-Level Modeling

ece695-2021

Programming and Assignment Material for ECE 695

embedded_ai

fp-diannao

fpga-zynqnet

FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS

gekko-strategies

Strategies to Gekko trading bot with backtests results and some useful tools.

gem5-cache-partitioning

Gem5 L2 Cache Partitioning

gem5valid_haswell

gpgpu-sim_uvmsmart

hi-dmm

Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis

implementation-of-amba-axi3-protocol

Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System Verilog simulator and the Mentor Graphics Veloce hardware emulator.

labpage

lenet5_hls

FPGA Accelerator for CNN using Vivado HLS

mafia

MAFIA: Multiple Application Framework for GPU architectures

marss

PTLsim and QEMU based Computer Architecture Research Simulator

marss-riscv

Micro-ARchitectural Full System Simulator for RISC-V