Topic: yosys Goto Github
Some thing interesting about yosys
Some thing interesting about yosys
yosys,Physical Design Flow from RTL to GDS using Opensource tools.
User: akilm
Home Page: https://www.vlsisystemdesign.com/
yosys,A basic verilog driver for the TM1638 LED and key matrix chip
User: alangarf
yosys,WIP open source tooling for the XC9500 / XC9500XL series of CPLDs from Xilinx.
User: anuejn
yosys,A eurorack-friendly audio frontend compatible with many FPGA boards.
Organization: apfelaudio
Home Page: https://apfelaudio.com/modules/pmod/
yosys,A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
User: ben-marshall
yosys,CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
Organization: cariboulabs
yosys,Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.
User: chili-chips-ba
Home Page: https://www.chili-chips.xyz/tetrisaraj
yosys,FPGA tool performance profiling
Organization: chipsalliance
Home Page: https://chipsalliance.github.io/fpga-tool-perf
yosys,Plugins for Yosys developed as part of the F4PGA project.
Organization: chipsalliance
Home Page: https://f4pga.org
yosys,Arduino compatible – Cortex M4F & FPGA Development Board
Organization: dadamachines
yosys,A blinky project for the ULX3S v3.0.3 FPGA board
User: doctorwkt
yosys,This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop
User: embedded-explorer
yosys,5 Day TCL begginer to advanced training workshop by VSD
User: fayizferosh
yosys,RISC-V RV32I CPU written in verilog
User: franzflasch
yosys,a collection of tools made while messing with the Colorlight 5A-75B V7.0 and some notes using ECP5 with Yosys
User: kittennbfive
yosys,[mirror] HDL development environment on Nix.
User: kivikakk
Home Page: https://hrzn.ee/kivikakk/hdx
yosys,Examples for the Lushay Labs tang nano 9k series
User: lushaylabs
Home Page: https://learn.lushaylabs.com/tang-nano-series/
yosys,RealtimeIO for LinuxCNC based on an FPGA
User: multigcs
yosys,draws an SVG schematic from a JSON netlist
User: nturley
yosys,Mostly AVR compatible FPGA soft-core
User: osresearch
yosys,Sipeed Tang Nano Fully Opensource Toolchain Ledblink
User: racerxdl
yosys,a project to check the FOSS synthesizers against vendors EDA tools
User: rodrigomelo9
yosys,SCARV: a side-channel hardened RISC-V platform
Organization: scarv
yosys,XCrypto: a cryptographic ISE for RISC-V
Organization: scarv
yosys,Example of how to get started with olofk/fusesoc.
User: sifferman
yosys,Sphinx Extension which generates various types of diagrams from Verilog code.
Organization: symbiflow
Home Page: https://sphinxcontrib-hdl-diagrams.rtfd.io
yosys,OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Organization: the-openroad-project
Home Page: https://openlane.readthedocs.io/
yosys,Trying to verify Verilog/VHDL designs with formal methods and tools
User: tmeissner
yosys,Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
User: tmeissner
yosys,A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator.
User: vmunoz82
yosys,Solving Sudokus using open source formal verification tools
User: vmunoz82
yosys,VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys).
User: vsdip
Home Page: https://www.vlsisystemdesign.com/vsd-ip-specs/
yosys,Unofficial Yosys WebAssembly packages
Organization: yowasp
Home Page: https://yowasp.org
yosys,SystemVerilog to Verilog conversion
User: zachjs
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