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quicklib

Quick development library (AutoMapper, LinQ, IOC Dependency Injection, MemoryCache, Scheduled tasks, Json and Yml Config and Options pattern, Serializers, etc) with crossplatform support for Delphi/Firemonkey (Windows,Linux,OSX/IOS/Android) and freepascal (Windows/Linux).

quickspi

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

r76firmware

DT5560SE firmwares and associated programs primarily designed for R76 for CDMS at UMN

read_the_docs

Projects and Labs for the Parallel Programming for FPGAs book

rfsoc_ofdm

PYNQ example of an OFDM Transmitter and Receiver on RFSoC.

rfsoc_opfb

A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC

rifl

ringbus4xilinx

ring bus IP for xilinx fpga

riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

rsacrack

A toolbox for extracting RSA private keys from public keys.

rsatool

rsatool can be used to calculate RSA and RSA-CRT parameters

rths

Real-Time Hardware Sorter, Using A Multi-Dimensional Sorting Algorithm

rtl-design-for-fpga

Engineering Program on RTL Design for FPGA Accelerator

s6_pcie_microblaze

PCI Express DIY hacking toolkit for Xilinx SP605. This repository is also home of Hyper-V Backdoor and Boot Backdoor, check readme for links and info

sc

Common libraries and data structures for C.

serial-studio

Multi-purpose serial data visualization & processing program

sharpwxdump

微信客户端取证，可获取用户个人信息(昵称/账号/手机/邮箱/数据库密钥(用来解密聊天记录))；支持获取多用户信息，不定期更新新版本偏移，目前支持所有新版本、正式版本

shellbox

shellbox is a shell with built-in commands for embedded systems.

simple-axi2ahb-bridge

AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc

simplevout

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

skid-buffer

Verilog Skid Buffer

skid_buffer

Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.

snickerdoodle-hls-data-mover

A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S defaults to 8 bits and AXI-MM to 64 bits)

soc_microblaze

Microblaze code and other code for Vivado and Vitis homework.

sokit

Sokit is a TCP & UDP package send / receive / transfer tool

spi-to-axi-bridge

An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

src

stb

stb single-file public domain libraries for C/C++

stereoscopic_comperator_ip

IP to produce a depth field from two AXI streams

stm32f107-lwip-rtl8201f