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sokit

Sokit is a TCP & UDP package send / receive / transfer tool

spi-to-axi-bridge

An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

stm32f107-lwip-rtl8201f

surf

A huge VHDL library for FPGA development

sv2v

SystemVerilog to Verilog conversion

tbps_crc

A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second

tooljet

Low-code platform for building business applications. Connect to databases, cloud storages, GraphQL, API endpoints, Airtable, Google sheets, OpenAI, etc and build apps using drag and drop application builder. Built using JavaScript/TypeScript. 🚀

uart-to-spi-bridge

UART, SPI and UART-To-SPI cores.

ustc-rvsoc

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

utils

verilog

verilog-axi

Verilog AXI components for FPGA implementation

verilog-axis

Verilog AXI stream components for FPGA implementation

verilog-cam

Verilog Content Addressable Memory Module

verilog-ethernet

Verilog Ethernet components for FPGA implementation

verilog-format

Verilog formatter

verilog-i2c

Verilog I2C interface for FPGA implementation

vhdl-axis-uart

UART to AXI Stream interface written in VHDL

vhdl_ip-cores

vhdlformatter

VHDL formatter web online written in typescript

vhdlproc

VHDLproc is a VHDL preprocessor

wb2axip

Bus bridges and other odds and ends

wishboneaxi

Wishbone to AXI bridge (VHDL)

wzab-hdl-library

This repository contains my small solutions related to HDL design.

xilinx-bram-wrapper

A flexible RAM wrapper for optimal BRAM utilization

xilinx-fpga-pcie-xdma-tutorial

Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核

xilinx-risc-v

Porting PicoRV32 to Artix-7 and Spartan-7. Generic vivado template for supported Xilinx FPGA is included.

xilinx-unprotect

xilinx-vhdl

xilinx_fpga_utils

my utility IP cores for Xilinx FPGAs