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shanyinshuiyue's Projects

logi-hard icon logi-hard

All Logi specific HDL code (platform specific interface, extension boards, specific hdl, etc)

logic icon logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

lwrb icon lwrb

Lightweight generic ring buffer manager library

lxp32-cpu icon lxp32-cpu

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

md2pdf icon md2pdf

Offline markdown to pdf, choose -> edit -> transform 🥂

meduram icon meduram

Multi-port BRAM IP for ASIC and FPGA

mlib icon mlib

Library of generic and type safe containers in pure C language (C99 or C11) for a wide collection of container (comparable to the C++ STL).

neo430 icon neo430

:computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

neorv32 icon neorv32

🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

netfpga icon netfpga

NetFPGA 1G infrastructure and gateware

oc-accel icon oc-accel

OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology

oh icon oh

Verilog library for ASIC and FPGA designers

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