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100-gcc-tips

A collection of gcc tips. 100 maybe just mean many here.

ad936x-filter-wizard

MATLAB-based FIR filter design

ad937x-filter-wizard

MATLAB-based FIR filter and profile designer

aib-protocols

amba_axi_ahb_apb

AMBA bus lecture material

antenna-array-analysis

A simple GUI tool for antenna array analysis

aq_mipi_csi2rx_ultrascaleplus

archivebox

🗃 Open source self-hosted web archiving. Takes URLs/browser history/bookmarks/Pocket/Pinboard/etc., saves HTML, JS, PDFs, media, and more...

arty_xjtag

Xilinx JTAG Toolchain on Digilent Arty board

async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

awesome-autohotkey

A curated list of awesome AutoHotkey libraries, library distributions, scripts, tools and resources.

awesome-cpp

A curated list of awesome C++ (or C) frameworks, libraries, resources, and shiny things. Inspired by awesome-... stuff.

awesome-embedded-software

:stars: List of software (HW interfaces, libs, protocols, etc) specifically suitable for resource-constrained Embedded Systems (low-memory and low-power) like 8-bit, 16-bit and 32-bit microcontrollers.

awesome-pascal

A curated list of awesome Delphi/FreePascal/(any)Pascal frameworks, libraries, resources, and shiny things. Inspired by awesome-... stuff. Open source and freeware only!

awgn_boxmuller

AWGN signal generator IP for FPGA implemented by Verilog HDL with Fmax up to 320MHz on Xilinx Virtex Ultra-Scale FPGA.

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

axi-uart-lite

axi4_master

A VHDL implementation of an AXI4 Master

axi4lite2uart

This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.

axi_if_converter

AXI Interface Converter (Stream, Memory-Mapped and Lite)

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

basic_verilog

Must-have verilog systemverilog modules

bitfield-c

Bit array parsing and encoding utility library in C

bitfiltrator

Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats

blackman_harris_win

Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CORDIC like as DDS (sine / cosine generator)

blog

Projects published on controlpaths.com and hackster.io

bonfire_axi

Bonfire toplevel with AXI4 Interfaces

boolking.github.io

blog

brianhg-ddr3-controller

DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

bsg_manycore

Tile based architecture designed for computing efficiency, scalability and generality