vlsi-eda / poc Goto Github PK

The unit "misc_strobegenerator.vhdl" is needed by io_7SegmentMux_BCD.vhdl module, but it is missing on github. Is it available elsewhere? Could someone check it in?

The parser for *.files and *.rules files does not report syntax errors.

Add a proper error reporting.

Implement PowerShell auto completion rules for poc.ps1.

Maybe it's possible to derive the completion rules from the internal ArgumentParser instance.

Related issues: #33

In the IP core components documentation, there is usage of namespace and sub-namespaces.

What is the meaning of namespace and sub-namespaces, its usage and how do I conceptualize it in the overall infrastructure of the code?

I think all components simply belong to POC library.

Why not to associate namespace name with the usage of libraries, and Sub-Namespace as appended to the Namespace name for the Library?

For example; Namespace is POC so make library POC,
and SubNamespace POC.Common, so make the library POCCommon.

Then at least the dependencies are more finely stated.

And then maybe one can also use context to wrap all sub-namespaces into the namespace.

1. Write the documentation in reST
2. Transform existing documentation from *.md files and wiki pages into reST
3. Add a flow to compile the documentation on ReadTheDocs.org

Import PoC IP cores into vendor tools.

• Altera Quartus incl. SDC files
• Xilinx ISE incl. UCF files
• Xilinx Vivado incl. XDC files

Enable the prompt use of PoC by an incremental configuration process that asks for configuration info only when a certain flow or tool is to be used for the first time. A modular organization of the configuration data appears to be the natural choice for such an approach. This would additionally enable a targeted reconfiguration, e.g., after the update of a specific vendor tool. An explicitly triggered complete configuration should still be possible.

Measures:

• Tools maintain a configuration state including the states unconfigured and configured (with the corresponding info).
• Each invocation of a tool would start with calling its ensureConfiguration method and trigger the tool configuration when the tool is in unconfigured state. The actual invocation will proceed when the tool already was or has been properly configured.
• The optional invocation of ./poc.sh configure walks the user through a possibly complete configuration. Each configuration step may be skipped by the choice of the user.
• The invocation ./poc.sh configure <tool> allows a targeted (re-)configuration of the named tool.

PoC's simulation commands should get a --reproducer flag to assemble all needed simulation files in a bugreport directory ready for packaging as a bug report. This might be needed to solve ghdl/ghdl#199.

Subtasks:

• Add a --reproducer switch to simulation commands.
• Copy all input files to temp\<simulator>\bugreport\<date|name>.
• Create matching (standalone) compile scripts.
• Optional:
  • Zip all files.

Add VHDL simulator support for Cadence Incisive.

The documentation already contains a section for a continuous change log.

All added, edited or removed items (packages, IP cores, features, ...) should reconstructed from Git log and added as a comprehensive items.

All active development branches are effected by a Travis build issue presumably introduced from the sphinx branch. Needs a fix so that it does not mask other errors introduced in the meanwhile.

I'm not able to compile the file "sim_waveform.vhdl" using Vivado (Version 2015.2).
I get the following errors:

ERROR: [VRFC 10-925] indexed name is not a time [/home/albert/git/dnk7/src/hw/PoC/sim/sim_waveform.vhdl:502]
ERROR: [VRFC 10-925] indexed name is not a time [/home/albert/git/dnk7/src/hw/PoC/sim/sim_waveform.vhdl:531]
ERROR: [VRFC 10-724] found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+" [/home/albert/git/dnk7/src/hw/PoC/sim/sim_waveform.vhdl:733]
ERROR: [VRFC 10-925] indexed name is not a time [/home/albert/git/dnk7/src/hw/PoC/sim/sim_waveform.vhdl:743]
ERROR: [VRFC 10-724] found '0' definitions of operator "&", cannot determine exact overloaded matching definition for "&" [/home/albert/git/dnk7/src/hw/PoC/sim/sim_waveform.vhdl:745]
ERROR: [VRFC 10-1471] type error near fs ; current type time; expected type real [/home/albert/git/dnk7/src/hw/PoC/sim/sim_waveform.vhdl:748]
ERROR: [VRFC 10-1471] type error near delay ; current type time; expected type real [/home/albert/git/dnk7/src/hw/PoC/sim/sim_waveform.vhdl:889]
ERROR: [VRFC 10-1471] type error near p ; current type time; expected type real [/home/albert/git/dnk7/src/hw/PoC/sim/sim_waveform.vhdl:976]

Any ideas?

On operating system GNU/Linux x86-64

my_config.vhdl is configured with the following lines:

constant MY_BOARD   : string := "Custom";
constant MY_DEVICE  : string := "xc7vx690t-2ffg1761";

my_project.vhdl is configured with the following lines:

constant MY_PROJECT_DIR       : string := "/home/adrien/Sandbox/poc-library/myproj/";
constant MY_OPERATING_SYSTEM  : string := "LINUX";

PoC-Library was configured with the command ./poc.sh --configure
Tools installed: Vivado 2015.1, GHDL and GTKWave

I tried to run the testbenches with the command: ./testbench.sh --ghdl PoC.arith.addw -v -l -d
An error occured, the terminal messages are the following:

[adrien] > ./testbench.sh --ghdl PoC.arith.addw -v -l -d
================================================================================
                    The PoC Library - Testbench Service Tool                    
================================================================================

DEBUG: Reading PoC configuration from '/home/adrien/Sandbox/poc-library/PoC/py/config.private.ini' and '/home/adrien/Sandbox/poc-library/PoC/py/config.public.ini'
DEBUG: Reading testbench configuration from '/home/adrien/Sandbox/poc-library/PoC/tb/configuration.ini'
PoC.arith.addw
  preparing simulation environment...
  Commands to be run:
  1. Change working directory to temporary directory
  2. Parse filelist file.
    a) For every file: Add the VHDL file to GHDL's compile cache.
  3. Compile simulation
  4. Run simulation
  ----------------------------------------
  cd "/home/adrien/Sandbox/poc-library/PoC/temp/ghdl"
DEBUG: Reading filelist '/home/adrien/Sandbox/poc-library/PoC/tb/arith/arith_addw_tb.files'
  running analysis for every vhdl file...

DEBUG: call ghdl: ['/usr/bin/ghdl', '-a', '-P.', '--syn-binding', '--std=93', '--work=poc', '/home/adrien/Sandbox/poc-library/PoC/tb/common/my_config_ML505.vhdl']
    command: /usr/bin/ghdl -a -P. --syn-binding --std=93 --work=poc /home/adrien/Sandbox/poc-library/PoC/tb/common/my_config_ML505.vhdl
ghdl messages for : /home/adrien/Sandbox/poc-library/PoC/tb/common/my_config_ML505.vhdl
--------------------------------------------------------------------------------
/home/adrien/Sandbox/poc-library/PoC/tb/common/my_config_ML505.vhdl:47:14:warning: package "my_config" does not require a body

DEBUG: call ghdl: ['/usr/bin/ghdl', '-a', '-P.', '--syn-binding', '--std=93', '--work=poc', '/home/adrien/Sandbox/poc-library/PoC/tb/common/my_project.vhdl']
    command: /usr/bin/ghdl -a -P. --syn-binding --std=93 --work=poc /home/adrien/Sandbox/poc-library/PoC/tb/common/my_project.vhdl
ghdl messages for : /home/adrien/Sandbox/poc-library/PoC/tb/common/my_project.vhdl
--------------------------------------------------------------------------------
/home/adrien/Sandbox/poc-library/PoC/tb/common/my_project.vhdl:50:14:warning: package "my_project" does not require a body

ERROR: This testbench requires some Xilinx Primitves. Please configure Xilinx ISE / Vivado

Please run 'poc.[sh/cmd] --configure' in PoC root directory.

The Sphinx documentation flow was extended by several sphinx and third party extensions. These extensions should be documented along with their modifications. A comprehensive syntax guide should be assembled, to collect all syntax notations at one place instead of dozens of third party documentation websites with partially poor usage descriptions.

Extensions list:

• Standard Sphinx extensions
  • sphinx.ext.autodoc
  • sphinx.ext.extlinks
  • sphinx.ext.intersphinx
  • sphinx.ext.inheritance_diagram
  • sphinx.ext.todo
  • sphinx.ext.graphviz
  • sphinx.ext.mathjax
  • sphinx.ext.ifconfig
  • sphinx.ext.viewcode
• SphinxContrib extensions
  • sphinxcontrib.wavedrom
  • autoapi.sphinx
• local extensions (patched)
  • autoprogram (derived from sphinxcontrib.autoprogram)
• local extensions
  • DocumentMember
  • PoC

Syntax:

• from docutils
• from Sphinx
• from Sphinx extensions
• from own extensions

Gitter.im is a chat platform for GitHub integration.

Subtasks:

• Test Gitter, if it fits the needs of PoC.
• Add the badge on the main README.md.

Travis-CI is a continues integration platform with GitHub integration.

Subtasks:

• Reach out to Travis-CI in Berlin and ask for VHDL/Verilog (GHDL, Icarus Verilog) integration.

At Enclustra, we have been considering open-sourcing our clock-crossing VHDL blocks and constraints files. However, I attended a presentation by @Paebbels at FPGA Conference Europe in Munich and I saw that PoC already provides these things.

I have personally used some of these PoC clock-crossing blocks in the past and found them to work well. Therefore, it would make sense for Enclustra to use the PoC blocks (and contribute to their maintenance), instead of maintaining different versions of basically the same logic.

However, there is just one thing that we are worried about: the lack of activity. There has been no release of PoC since 2017, some GitHub issues have remained open for years, and there has been no visible development for years. So, what is the status of this library?

I think @Paebbels mentioned that there was a lot of internal development that will hopefully be released sometime soon. Is there any plan for when this release might happen? And why can't I see this development in any of the Git branches?

The Quick Start Guide lists Python 3 as a dependency, but it misses a list of Package dependencies, which could be installed from PyPI.

Work Items:

• Check if the Quick Start Guide links to the full documentation.
• Check if the full documentation contains all Python dependencies.
• Add a hint how to fulfill all Python dependencies via pip.
• List Python dependencies for other flows:
  • Appveyor
  • ReadTheDocs
  • Travis-CI
• Register PoC at Requires.io to check if Python dependencies are up-to-date.

Currently, the compile order of VHDL files relies on the definition order of VHDL source files in the *.files files. The Python-based infrastructure should be able to calculate this order on its own.

Tools that require pre-ordered VHDL file lists or per-file commands executed in the right order:

• Simulators

  • Aldec Active-HDL
  • GHDL
  • Mentor Graphics ModelSim
  • Mentor Graphics QuestaSim
  • ISE Simulator if used in a per-file mode
  • Vivado Simulator if used in a per-file mode

• Compiler

I don't think that many will find the News section enlightening:

News
13.05.2016 - PoC 1.0.0 was released.
Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet

hi everyone.
i faced with pyIPCMI problem. somebody can help me?
how can i solve this problem?

i referenced POC library document 1.2.0. and exactly followed chap 5.1 to 5.4.1.

The simulation packages are not (and will not) be supported by Xilinx ISE, because of a bad shared variable implementation. We will drop the support for VHDL-93 testbenches. We still hope for a correct VHDL-2008 in future Xilinx Vivado Simulator releases.

Work Items:

1. Remove files:
   • sim_random.v93.vhdl
   • sim_simulation.v93.vhdl
   • sim_unprotected.v93.vhdl
2. alter and review *.files files.
3. remove wrappers
   • sim_random.v08.vhdl - remove commented wrappers ("procedural interface")
   • sim_simulation.v08.vhdl
4. Rename globalSimulationStatus to globalSimStatus or SimStatus
   As all global VHDL-93 variables are removed (prefixed with global_) the name can be chooses shorter.
   • alter sim_simulation.v08.vhdl and sim_waveform.vhdl
   • review all testbenches
5. Write a PoC.arith.prng testbench for Xilinx ISE Simulator without simulation package helper usage, so the Python infrastructure can still be tested with this testbench.
   • Manual assertion counting
   • Manual report generation [PASSED | FAILED]

During the synthesis step the uart_bclk is being removed. I'm using Vivado 2016.2

I get the following relevant outputs:

INFO: [Synth 8-4471] merging register 'blkUART.uart_bclk/bclk_x8_r_reg' into 'blkUART.uart_bclk/bclk_r_reg' [/home/albert/git/dnk7/src/hw/PoC/src/io/uart/uart_bclk.vhdl:104]
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\blkUART.uart_bclk/bclk_r_reg )
WARNING: [Synth 8-3332] Sequential element (blkUART.uart_bclk/bclk_r_reg) is unused and will be removed from module kc705_top.

This is how I instantiate the component:

        uart_bclk : entity PoC.uart_bclk
        generic map (
            CLOCK_FREQ => 50 MHz
        )
        port map (
            clk         => clk_comp,
            rst         => rst,
            bclk        => bclk,
            bclk_x8 => bclk_x8
        );

The following alternative solution works fine:

    bclk_gen_x8: entity PoC.arith_counter_free
      generic map (
        DIVIDER => 50000000/(8*115200)
      )
      port map (
        clk => clk_comp,
        rst => '0',
        inc => '1',
        stb => bclk_x8
      );
    bclk_gen_x1: entity PoC.arith_counter_free
      generic map (
        DIVIDER => 8
      )
      port map (
        clk => clk_comp,
        rst => '0',
        inc => bclk_x8,
        stb => bclk
      );

PoC currently provides only an adapter which maps between the PoC.Mem interface and the native interface of the Xilinx MIG IP core. This adapter must be instantiated together with the netlist generated by the Xilinx IP core generator. PoC already supports netlist generation using Xilinx ISE (IP core PoC.xil.mig.KC705_MT8JTF12864HZ_1G6). An XCI file for Xilinx Vivado can be found in PoC-Examples.

Requested features:

1. The temperature monitor should be excluded by default, when the MIG IP core is generated using Xilinx ISE. The device temperature should be provided by another PoC IP core, see #30.

2. Provide a XCI file for Xilinx Vivado. Netlist generation should allow a configurable user clock frequency, because the clock for the native interface is provided by the MIG IP core itself. The temperature monitor should be excluded, as above.

3. Implement a wrapper instantiating the adapter and the netlist:

   • Suggested name: "ddr3_ctrl_KC705" or "ddr3_wrapper_KC705".

   • User side interface: PoC.Mem interface and device temperature.

   • DDR3 side interface: as required by the MIG IP core. Note: the top-level DDR3 port names must match that of the MIG IP core because the MIG generates constraints also for the top-level ports (IO standard, slew rate, ...). The constraints could not be adapted because Vivado embeds them in the generated design checkpoint.

   • Configuration parameter: DIMM : string selecting the proper IP core configuration (DIMM timing) from PoC.xil.mig. Alternatively, the timing should be configurable during netlist generation.

   • For Vivado, the netlist must be instantiated using a component declaration.

Related: update memory test and cache test examples in PoC-Examples.

Implement Bash auto completion rules for poc.sh.

Maybe it's possible to derive the completion rules from the internal ArgumentParser instance.

Related issues: #34

Some Submodule paths, named pyIPCMI and uvvm failed when cloning recursive.

Landscape.io is a Python code quality checker.

Subtasks:

• Investigate how it works and if it fits the needs of PoC.
• Does it iteract well with GitHub?
• How good are the reports?

Add synthesizer support for Synopsys Synplify Pro.

Note:
Synplify is also included in Lattice Diamond and can be used as an alternative to the Lattice Synthesis Engine.

Currently, the complete working directory of a tool is deleted before a new run. This behavior creates issues on Linux (invalid inode) and Windows (access denied, directory is used).

Solution 1 - purge the working directory by:

• deleting all sub-directories
• deleting all files

Hey,
it would be nice, if you could provide a precompiled binary for ghdl.

Thanks
Franz

The GitHub wiki is no longer needed.
All documentation is now hosted on ReadTheDocs at poc-library.rtfd.io.

Work Items:

• Delete the GitHub wiki contents.
• Setup a dummy wiki site redirecting to the official documentation.

The new main documentation is hosted on ReadTheDocs. The README.md in PoC's root directory can now be shortened to a quick guide and point to the matching sections in the main documentation at RTFD.

Work Items:

• rework README.md
• search the repository for other READMEs which should point to RTFD

PowerShell has the ability to provide user-defined drives. PoC should provide a drive called poc. This allows fast access (and tab completion) to IP cores, testbenches and constraint files. Normal CmdLets like dir and cd could be used to browse PoC's IP core database.

Possible output:

dir poc:\io\ddrio

PoC Entity             Source file         VHDL name
----------------------------------------------------
Package ddrio          ddrio.pkg.vhdl      ddrio
PoC.io.ddrio.in        ddrio_in.vhdl       ddrio_in
PoC.io.ddrio.inout     ddrio_inout.vhdl    ddrio_inout
PoC.io.ddrio.out       ddrio_out.vhdl      ddrio_out

I want to use the function raw_format_slv_hex from string.vhdl.
Vivado 2016.2 gives an error on line 359 about the following

Value := resize(slv, Value'length);

Error message is

[Synth 8-2778] type error near resize ; expected type std_logic_vector

How to fix ? Is it specific to Vivado ?

Brahim @ DCT :: DSI

Currently, poc.ps1 configure will overwrite an existing config.private.ini file.

Proposed new behavior:

• create a backup file (including date/time stamp?)
  • config.private.ini.bak -> overwrite existing backup files
  • config.private.2016-11-27.ini
  • config.private.2016-11-27#14-38-19.ini
• log the backup file's name in the program output if in verbose or debug mode

The IP core io_FanControl currently wraps a device-specific system monitor. This monitor in turn instantiates a device specific XADC which monitors the device temperature. But, the device temperature is also required for other IP cores, e.g., the Xilinx DDR3 memory controller on the KC705 board.

To solve this:

• either an output "device_temp" should be added to the io_FanControl and system monitor IP cores,

• or a separate temperature monitor IP core should be implemented which provides the necessary inputs for io_FanControl and other IP cores like memory controllers.

Add synthesizer support for Mentor Graphics Precision-RTL.

The zip files provided by GitHub doesn't contain submodule files.

Working Items:

• Create a Travis-CI based build flow, to package zip files for every tagged release, which also contain submodule files of the correct submodule commit state.
• Link these bundled zip files in the download documentation (RTFD, README) instead of GitHubs automatic zip files.

I need to send 1st two randomised input data into input transaction and reset =1and then reset=0.after 65th clock cycle i have to check divider output.
i am using this testbench format: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_par2_cocotb.py
but reset is not toggling for every input it is constant =1.
how to toggle reset bit in this testbench.

Currently the Python infrastructure is only tested on a Linux platform (Travis-CI: Ubuntu). AppVeyor can be used for free, which provides a Windows Server 2012 R2 platform for CI testing.

As pull request #24 shows, PoC has a list of required or recommended project settings for each supported vendor tool chain. These should be documented on RTFD.

• Xilinx ISE:

  • --use_new_parser yes
  • Add IP core search directories: -sd <pathes>

• Xilinx Vivado:

  • Enable assert statements via Tcl or GUI.

Hi,
when configuring PoC for Intel Modelsim Starter Edition, I encountered the following problem:

Configuring installed tools
---------------------------
Configuring PoC
  Installation directory: /home/johannes/tries/foss-applications/PoC (found in environment variable)
Configuring Git
  Is Git installed on your system? [Y/n/p]: Y
  Git installation directory [/usr/bin]: /usr/bin
  Install Git mechanisms for PoC developers? [y/N/p]: N
  Git is now configured.
Configuring Aldec
  Are Aldec products installed on your system? [Y/n/p]: n
  Aldec is now configured.
Configuring Altera
  Are Altera products installed on your system? [Y/n/p]: n
Configuring Intel
  Are Intel products installed on your system? [Y/n/p]: Y
  Intel installation directory [/opt/Intel]: /home/johannes/local_programs/intelFPGA_lite
Configuring Intel Quartus
  Is Intel Quartus Prime installed on your system? [Y/n/p]: y
  16.1 version [16.1]: 17.0
  Intel Quartus installation directory [/home/johannes/local_programs/intelFPGA_lite/17.0/quartus]: /home/johannes/local_programs/intelFPGA_lite/17.0/quartus
  Checking Altera Quartus version... (this may take a few seconds)
  Intel Quartus Prime is now configured.
Configuring Intel ModelSim
  Is ModelSim Intel Edition installed on your system? [Y/n/p]: y
FATAL: An unknown or unhandled exception reached the topmost exception handler!
  Exception type:      TypeError
  Exception message:   _ConfigureEdition() takes 1 positional argument but 3 were given
  Caused by:         _ConfigureEdition in file '/home/johannes/tries/foss-applications/PoC/py/ToolChains/Intel/ModelSim.py' at line 113
--------------------------------------------------------------------------------
  File "/home/johannes/tries/foss-applications/PoC/py/PoC.py", line 1247, in main
    poc.Run()
  File "/home/johannes/tries/foss-applications/PoC/py/PoC.py", line 368, in Run
    ArgParseMixin.Run(self)
  File "/home/johannes/tries/foss-applications/PoC/py/lib/pyAttribute/ArgParseAttributes.py", line 181, in Run
    args.func(self, args)
  File "/home/johannes/tries/foss-applications/PoC/py/PoC.py", line 443, in HandleConfiguration
    configurator.ConfigureAll()
  File "/home/johannes/tries/foss-applications/PoC/py/ToolChains/__init__.py", line 775, in ConfigureAll
    self._ConfigureTools(self._configurators)
  File "/home/johannes/tries/foss-applications/PoC/py/ToolChains/__init__.py", line 846, in _ConfigureTools
    self._ConfigurationLoop(configurator)
  File "/home/johannes/tries/foss-applications/PoC/py/ToolChains/__init__.py", line 899, in _ConfigurationLoop
    elif (self._host.Platform == "Linux"):    configurator.ConfigureForLinux()
  File "/home/johannes/tries/foss-applications/PoC/py/ToolChains/__init__.py", line 280, in ConfigureForLinux
    self.ConfigureForAll()
  File "/home/johannes/tries/foss-applications/PoC/py/ToolChains/Intel/ModelSim.py", line 92, in ConfigureForAll
    changed,edition = self._ConfigureEdition()
  File "/home/johannes/tries/foss-applications/PoC/py/ToolChains/Intel/ModelSim.py", line 113, in _ConfigureEdition
    edition =         super()._ConfigureEdition(IntelModelSimEditions, defaultEdition)
--------------------------------------------------------------------------------
Please report this bug at GitHub: https://github.com/VLSI-EDA/PoC/issues
--------------------------------------------------------------------------------

I looked for the cause and found the following workaround (same as it's done in the respective files for Altera):

diff --git a/py/ToolChains/Intel/ModelSim.py b/py/ToolChains/Intel/ModelSim.py
index b1476f2..bae782a 100644
--- a/py/ToolChains/Intel/ModelSim.py
+++ b/py/ToolChains/Intel/ModelSim.py
@@ -34,7 +34,7 @@ from subprocess                   import check_output
 
 from lib.Functions                import Init
 from ToolChains                   import ConfigurationException, EditionDescription, Edition
-from ToolChains.Mentor.ModelSim   import ModelSimException as Mentor_ModelSimException, ModelSimPEConfiguration as Mentor_ModelSim_Configuration
+from ToolChains.Mentor.ModelSim   import ModelSimException as Mentor_ModelSimException, Configuration as Mentor_ModelSim_Configuration
 from ToolChains.Intel             import IntelException
 
 
@@ -89,14 +89,14 @@ class Configuration(Mentor_ModelSim_Configuration):
 				self.ClearSection()
 			else:
 				# Configure ModelSim version
-				edition = self._ConfigureEdition()
+				changed,edition = self._ConfigureEdition()
 
 
 				configSection = self._host.PoCConfig[self._section]
 				if (edition is IntelModelSimEditions.ModelSimIntelEdition):
 					configSection['InstallationDirectory'] = self._host.PoCConfig.get(self._section, 'InstallationDirectory', raw=True).replace("_ase", "_ae")
 				elif (edition is IntelModelSimEditions.ModelSimIntelStarterEdition):
-					configSection['InstallationDirectory'] = self._host.PoCConfig.get(self._section, 'InstallationDirectory', raw=True).replace("_ase", "_ase")
+					configSection['InstallationDirectory'] = self._host.PoCConfig.get(self._section, 'InstallationDirectory', raw=True).replace("_ae", "_ase")
 
 				self._ConfigureInstallationDirectory()
 				binPath = self._ConfigureBinaryDirectory()

This furthermore fixes the default installation path ("ase" instead of "ae" for starter edition of modelsim). If you prefer a pull request over the patch, just let me know.

In the README.md of the fifo folder a FIFO for dependent clocks is mentioned but the corresponding file fifo_dc_got.vhdl is missing.

Hello,

I tried to setup PoC as described in the Quickstart Guide in the readme. After experiencing the bug described in #62 and applying the suggested fix (renaming PoC.py in the submodule) the following error occured during configuration:

FATAL: An unknown or unhandled exception reached the topmost exception handler!
  Exception type:      KeyError
  Exception message:   'INSTALL.Intel.Quartus'
  Caused in:           __getitem__ in file '/usr/lib64/python3.6/configparser.py' at line 959
--------------------------------------------------------------------------------
  File "/home/bcmdev/dev/PoC/lib/pyIPCMI/FrontEnd.py", line 86, in main
    pyIPCMI.Run()
  File "/home/bcmdev/dev/PoC/lib/pyIPCMI/pyIPCMI/__init__.py", line 406, in Run
    ArgParseMixin.Run(self)
  File "/home/bcmdev/dev/PoC/lib/pyIPCMI/lib/pyAttribute/ArgParseAttributes.py", line 187, in Run
    args.func(self, args)
  File "/home/bcmdev/dev/PoC/lib/pyIPCMI/pyIPCMI/__init__.py", line 503, in HandleConfiguration
    configurator.ConfigureAll()
  File "/home/bcmdev/dev/PoC/lib/pyIPCMI/pyIPCMI/ToolChain/__init__.py", line 798, in ConfigureAll
    self._ConfigureTools(self._configurators)
  File "/home/bcmdev/dev/PoC/lib/pyIPCMI/pyIPCMI/ToolChain/__init__.py", line 898, in _ConfigureTools
    self._ConfigureDefaultTools()
  File "/home/bcmdev/dev/PoC/lib/pyIPCMI/pyIPCMI/ToolChain/__init__.py", line 944, in _ConfigureDefaultTools
    selector.Select()
  File "/home/bcmdev/dev/PoC/lib/pyIPCMI/pyIPCMI/ToolChain/Altera/Quartus.py", line 149, in Select
    editions = self._GetConfiguredEditions(QuartusEditions)
  File "/home/bcmdev/dev/PoC/lib/pyIPCMI/pyIPCMI/ToolChain/__init__.py", line 666, in _GetConfiguredEditions
    if (len(self._host.Config[edition.Section]) > 0):
  File "/usr/lib64/python3.6/configparser.py", line 959, in __getitem__
    raise KeyError(key)
--------------------------------------------------------------------------------
Please report this bug at GitHub: https://github.com/VLSI-EDA/pyIPCMI/issues

Steps to reproduce:

1. Download PoC via git clone --recursive
2. Rename mv lib/pyIPCMI/pyIPCMI/ToolChain/PoC.py lib/pyIPCMI/pyIPCMI/ToolChain/pyIPCMI.py
3. Run configuration script:

./poc.sh configure
================================================================================
                             pyIPCMI - Service Tool
================================================================================
No private configuration found. Generating an empty pyIPCMI configuration...
Explanation of abbreviations:
  Y - yes      P        - pass (jump to next question)
  N - no       Ctrl + C - abort (no changes are saved)
Upper case or value in '[...]' means default value
--------------------------------------------------------------------------------

Configuring installed tools
---------------------------
Configuring PoC
  Installation directory: /home/bcmdev/dev/PoC/lib/pyIPCMI (found in environment variable)
Configuring Git
  Is Git installed on your system? [Y/n/p]: Y
  Git installation directory [/usr/bin]: /usr/bin
  Install Git mechanisms for pyIPCMI developers? [y/N/p]: N
  Git is now configured.
Configuring Aldec
  Are Aldec products installed on your system? [Y/n/p]: n
  Aldec is now configured.
Configuring Altera
  Are Altera products installed on your system? [Y/n/p]: n
Configuring Intel
  Are Intel products installed on your system? [Y/n/p]: Y
  Intel installation directory [/opt/IntelFPGA]: /opt/quartus
Configuring Intel Quartus Prime
  Is Intel Quartus Prime installed on your system? [Y/n/p]: Y
  17.0 version [17.0]: 18.1
  Intel Quartus Prime installation directory [/opt/quartus/18.1/quartus]: /opt/quartus/18.1/quartus
  Checking Altera Quartus version... (this may take a few seconds)
  Intel Quartus Prime is now configured.
Configuring Intel Quartus Prime Lite
  Is Intel Quartus Prime installed on your system? [Y/n/p]: n
Configuring Intel ModelSim
  Is ModelSim Intel Edition installed on your system? [Y/n/p]: n
Configuring Intel ModelSim (Starter Edition)
  Is ModelSim Intel Edition installed on your system? [Y/n/p]: n
Configuring Lattice
  Are Lattice products installed on your system? [Y/n/p]: n
Configuring Mentor
  Are Mentor products installed on your system? [Y/n/p]: n
Configuring Xilinx
  Are Xilinx products installed on your system? [Y/n/p]: n
Configuring GHDL
  Is GHDL installed on your system? [Y/n/p]: n

Configure default tools? [Y/n]: Y
Choosing default tools

Any help would be greatly appreciated.

The current auto generated help page and sub-help pages are not good. The argparse help page generators should be replaced to:

• Create the list of commands in deterministic order
• Use wider columns

Hello Guys ...

I don't know if this is a real issue. But while i'm reading the documentation i noticed that there where multiple examples the same.

More precisely the file 'PoC/docs/UsingPoC/Synthesis.rst' contains multiple occurrences of '.\poc.ps1 quartus PoC.arith.prng --board=DE4' from the quartus example.

Thank you for your time and best regards

Dear,

do you know how to define the use of 512 word 16bit RAM (preloaded during FPGA power on and acting as ROM)
in vhdl (using GHDL & Yosys) for FPGA e.g. ICE40 ?

Hoping to receive some help, I remain,

Patrick Pelgrims

Xilinx Vivado uses a new IP-XACT-based file format (*.xci) to describe IP cores in their IP catalog. PoC needs to support the extraction of source codes and generation of netlists from these files.

Note:
PoC can already handle Xilinx Core Generator files (*.xco) from Xilinx ISE.

Add simulator support for Aldec Riviera-PRO.

Work Items:

• Simulator layer
  • Derive RivieraPROSimulator module from ModelSimSimulator module
• ToolChain Abstraction Layer
  • Derive RivieraPRO from ModelSimSimulator
    • Implement VHDLLibraryTool abstraction (vlib)
    • Implement VHDLCompiler abstraction (vcom)
    • Implement VHDLSimulator abstraction (vsim)
    • Implement output filters for
      • VHDLLibraryTool - vlib
      • VHDLCompiler - vcom
      • VHDLSimulator - vsim
• Implement a new Riviera-PRO command in PoC.py
  • add a rpro command line command and handler
• Add Riviera-PRO pre-compile support in pre-compile scripts for:
  • Altera
  • Intel
  • Lattice
  • Xilinx ISE
  • Xilinx Vivado

Create a my_project.vhdl file in tb/common/ after successful configuration.