Topic: verilog-project Goto Github
Some thing interesting about verilog-project
Some thing interesting about verilog-project
verilog-project,My experiments with Nexys4 DDR Artix-7 FPGA Board
User: 7entropy7
verilog-project,DDR2 memory controller written in Verilog
User: adibis
verilog-project,An 8 input interrupt controller written in Verilog.
User: adibis
verilog-project,
User: aekanshd
verilog-project,30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!
User: akashtailor-exe
verilog-project,EE4415 Project : AES Verilog
User: anand270294
verilog-project,the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
User: arjun-narula
verilog-project,Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
User: ashishrana160796
verilog-project,Hardware Viterbi Decoder in verilog
User: coole198669
verilog-project,SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol
User: cw1997
verilog-project,Transmitter and Receiver FPGAs connected using the UART Protocol to execute arithmetic operations and display the inputs on the transmitter's 7 Segment Display as well as the result on the Receiver's 7 Segments Display.
User: djzenma
verilog-project,Practices related to the fundamental level of the programming language Verilog.
User: emrealci
verilog-project,16 bit serial multiplier in SystemVerilog
User: flasonil
verilog-project,Image Processing Toolbox in Verilog using Basys3 FPGA
User: gowtham1729
verilog-project,This is the final project of Digital Systems Fall 2019@ University of Toronto
User: jiachen-meng
verilog-project,16 bit CPU created in Vivado with Verilog
User: lorentsinani
verilog-project,Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic
User: luk3sky
verilog-project,BUAA Computer Organization Project8 FPGA
User: lutingwang
verilog-project,Digital computer structure, Hardware Design Lab & Introduction to Computers for computer engineering projects in C, C#, Assembly, Pspice.
User: maorassayag
verilog-project,Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
User: michaelehab
verilog-project,Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
User: mihir8181
verilog-project,Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be effectively used to implement FIR, IIR and FFT type.The DA logic replaces the MAC operation of convolution summation o into a bit-serial look-up table read and addition operation .
User: mnmhdanas
verilog-project,Router 1 x 3 verilog implementation
User: mnmhdanas
verilog-project,UART - RTL Design and Verification
User: mnmhdanas
verilog-project,Implementing Different Adder Structures in Verilog
User: mongrelgem
verilog-project,5-stage pipelined 32-bit MIPS microprocessor in Verilog
User: neelkshah
verilog-project,Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog
User: nidhinchandran47
verilog-project,
User: pa-tiq
verilog-project,Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI bus provides a synchronized serial link with performance in MHz range.The project implements the bridge between the two protocols and serves as an interface between these two which allow direct communication and a solution to reduce development time and cost for complex embedded systems.
User: pendkeomkar
verilog-project,A verilog HDL based project to control a servomotor with voice commands from an android phone.
User: powerplayer9
verilog-project,The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.
User: prajwalgekkouga
verilog-project,Voting machine implemented in verilog
User: pratikbhuran
verilog-project,Taurus 3001 RISC-V 64-bit Privileged Minimal System Processor for T110/T28 ASIC
Organization: rismicrodevices
verilog-project,This repository contains all labs done as a part of the Embedded Logic and Design course.
User: sarthak268
verilog-project,Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier
User: snbk001
verilog-project,Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM
User: sudhamshu091
verilog-project,Simple Pipelined 32 bit RISC Processor
User: sudhamshu091
verilog-project,Single Cycle MIPS Pipelined Processor using Verilog
User: sudhamshu091
verilog-project,Single Cycle RISC MIPS Processor
User: sudhamshu091
verilog-project,Digital System Design Project - Spring 2020
User: tarlaun
verilog-project,RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.
User: tatan432
verilog-project,This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.
User: thesupercd
verilog-project,👻 Simple Undertale-like game on Basys3 FPGA written in Verilog
User: tongplw
verilog-project,miniSpartan6+ (Spartan6) FPGA based MP3 Player
User: ultraembedded
verilog-project,Cache compression using BASE-DELTA-IMMEDIATE process in verilog
User: vasanthkumar18
verilog-project,Solution to COA LAB Assgn, IIT Kharagpur
User: vedic-partap
verilog-project,Risc-V 32i processor written in the Verilog HDL
User: vsasakiv
verilog-project,NSCSCC2022龙芯杯个人赛,MIPS32,59MHz经典五级流水线架构,易于初学者阅读(计算机组成原理,自己动手写CPU)
User: xiazhuo
verilog-project,Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
User: zslwyuan
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