Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog
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Repository for Verilog, VHDL, System Verilog building blocks
We will upload very basic rtl project
Most of these are well tested and shouldn't have issues.
If you notice any issues,please raise it.
| 1 | JK FLIPFLOP |
| 2 | T FLIPFLOP |
| 3 | FULL ADDER |
| 4 | RIPPLE CARRY ADDER |
| 5 | MULTIPLEXERS |
| 6 | DEMULTIPLEXER |
| 7 | DECODER |
| 8 | ENCODER |
| 9 | PRIORITY ENCODER |
Hello, I believe there is a problem with the seven segment decoder when the input is 6. The current output is 0x75 which is 1110101 which implies that the signals b and d should be off while only b should be off and so the output should be 0x7d.
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