This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs
This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs
Design - Xilinx Vivado 2017
Verification - Python 3.6 for scripting and Xilinx ISE 14.7 command line tools.
Has this work been mentioned in any formal paper ?
I want to reference it.
I would like to ask if there is any documentation - paper in which your convolver architecture was based.
Hi. The module for c_shift_ram_0 is not present in the repository. It will be really helpful if you can provide with the code or maybe the logic behind how it is implemented. Thanks in advance.
hello , i am very interested in your job. But when i run the project in Vivado , i find the ip_data.txt and tb_op.txt missing. If the files can be shared will be appreciated.
hello，I want to ask where is the module c_shift_ram_0 in convolver？ thanks！
c_shift_ram file is not available in the source folder.
Hey, what should the ip_data.txt look like? Are the values in int format?
谢谢楼主!有机会可以发邮箱交流下：[email protected]
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