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accdnn

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

accelerating-cnn-with-fpga

This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.

azpr_cpu

用Altera FPGA芯片自制CPU

barvinn

BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/

bigpulp

⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform

bilinear

Bilinear interpolation realizes image scaling based on FPGA

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

cnn-accelerator

Hardware accelerator for convolutional neural networks

cnn-accelerator-vlsi

Convolutional accelerator kernel, target ASIC & FPGA

cnn-fpga

Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database

cnn_hardware_acclerator_for_fpga

This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

convolution_network_on_fpga

CNN acceleration on virtex-7 FPGA with verilog HDL

dana

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

deep-neural-network-hardware-accelerator

My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket

des_hardware_accelerator

Hardware acceleration combines the flexibility of general-purpose processors, such as CPUs, with the efficiency of fully customized hardware, such as GPUs and ASICs, increasing efficiency by orders of magnitude when any application is implemented higher up the hierarchy of digital computing systems

detecthumanfaces

Real time face detection based on Arm Cortex-M3 DesignStart and FPGA

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

e203_hbirdv2

The Ultra-Low Power RISC-V Core

fadec

fpga-imaging-library

An open source library for image processing on FPGA.

fpga-ml-accelerator

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

fpga-proj

FPGA project

fpga-stereo-camera-basys3

Integration of two camera modules to Basys 3 FPGA

fpga_based_cnn

FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.

fpga_design

这是我所开发的两个项目，包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统

fpgaandcnn

基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现

fpgabasedhighperformancetargetchecking

it is a set for all the respository of the project.

gnn-arch

[ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)

hackster

Files used with hackster examples

hand-writing-digital-recognization-based-on-fpga

Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The SoC worked not bad in the end the success rate up to 90%。.