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tritonmacroplace

Macro placement tool for OpenROAD flow

tritonroute

UCSD Detailed Router

tritonsizer

UCSD Sizer for leakage/dynamic power recovery, timing recovery

tuhdo.github.io

Emacs Mini Manual

tutorials

u-boot

Clone of upstream U-Boot repo with patches for Arm development boards

uart_exameple_linux

ubuntu-desktop

Ubuntu Desktop (LXDE) Dockerfile for trusted automated Docker builds.

ubuntu-live-remaster

ubuntu-make

Easy setup of common tools for developers on Ubuntu.

ubuntu-universal-ppas-collection

This repository contains collection of customized, updated, ported and backported packages for last LTS releases and latest pre-LTS release.

uc-os3

µC/OS-III is a preemptive, highly portable, and scalable real-time kernel. Designed for ease of use on a huge number of CPU architectures.

unicode.vim

A Vim plugin that provides a completion function for Unicode glyphs

use_vim_as_ide

use vim as IDE

uvm

UVM examples and projects

uvm-1

Mirror of the Universal Verification Methodology from sourceforge

uvm-lib-kits

uvm-symbiflow

uvmbasics

Basics of UVM via an APB slave

uvmprimer

Contains the code examples from The UVM Primer Book sorted by chapters.

uvmreference

Reference examples and short projects using UVM Methodology

vcddiff

Basic VCD comparison tool, for Verilator testing

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.

verible-linter-action

Automatic SystemVerilog linting in github actions with the help of Verible

verificationexcellence.github.io

Verification Excellence Knowledge Sharing

verilator

Verilator open-source SystemVerilog simulator and lint system

verilator-announce

Announcements related to Verilator

verilator_ext_tests

Extended and external tests for Verilator testing

verilog

Verilog HDL Codes

verilog-arbiter

A look ahead, round-robing parametrized arbiter written in Verilog.