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Frank.Q.Shan's Projects

riscv-qemu icon riscv-qemu

QEMU with RISC-V (RV64G, RV32G) Emulation Support

riscv-simulator icon riscv-simulator

💻 RISC-V Simulator of RV32I ISA. Out-of-order execution with Tomasulo algorithm and Speculation. Now with detailed runtime information and a full report on this project.

riscv-v-spec icon riscv-v-spec

Working draft of the proposed RISC-V V vector extension

riscv_vhdl icon riscv_vhdl

VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".

rocket-tools icon rocket-tools

Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)

rose icon rose

Developed at Lawrence Livermore National Laboratory (LLNL), ROSE is an open source compiler infrastructure to build source-to-source program transformation and analysis tools for large-scale C (C89 and C98), C++ (C++98 and C++11), UPC, Fortran (77/95/2003), OpenMP, Java, Python and PHP applications.

rowhammer icon rowhammer

Source code for testing the Row Hammer error mechanism in DRAM devices. Described in the ISCA 2014 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_isca14.pdf.

rramspec icon rramspec

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

rt-thread icon rt-thread

RT-Thread is an open source IoT operating system.

rtags icon rtags

A client/server indexer for c/c++/objc[++] with integration for Emacs based on clang.

rtc icon rtc

Real Time Clock with subsecond timer support

rtems icon rtems

Realtime SMP Kernel, networking, file-systems, drivers, BSPs, samples, and testsuite.

rtl2booksim icon rtl2booksim

Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.

rust icon rust

Empowering everyone to build reliable and efficient software.

sa-pcb icon sa-pcb

Annealing-based PCB placement tool

sbt icon sbt

sbt, the interactive build tool

sbt-ctags-ceedubs icon sbt-ctags-ceedubs

SBT ctags is an SBT plugin that will generate ctags for your Scala project.

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