The Plasma AXI-based System-on-Chip (Plasma-SoC) is an extension of Steve Rhoads' Plasma MLite Core, a processor that implements MIPS I with a small subset of Coprocessor 0 in order to provide limited support for interrupts and system calls. As its name implies, the cores of the Plasma-SoC rely on ARM AMBA4 Advanced eXtensible Interfaces (AXI) for communication over a configurable AXI4-Full Crossbar Interconnect.

The major hardware components of the Plasma-SoC consist of a CPU, Timer, Interrupt Controller, GPIO, UART, Interconnect, and an example design created to run on the Digilent Nexys4 board and another for the Xilinx VC707 Evalulation Kit. The software includes hardware drivers, FreeRTOS port, ICSP bootloader, Threadmetric Benchmark port, and several other examples to test and demonstrate the hardware's functionality. There are also several utility programs not intended to run on the hardware.

Take note of the Plasma-SoC's file structure shown below. For the sake of brevity, many of the sources are omitted from the structure. However, understand that the files not shown are still needed. Please see the sources themselves for more information.

• hdl --- All the VHDL hardware sources.
  • plasma --- Steve Rhoads' Plasma MLite Core.
  • plasoc --- Plasma-SoC cores, such as peripherals and interconnect.
    • plasoc_cpu.vhd --- CPU Core. Consists of the MLite Core and Configurable Associative/Direct Write-Back Cache.
    • plasoc_cross.vhd --- Crossbar Core. This core acts as the Plasma-SoC's interconnect. A wrapper should be generated instead of instantiating this core directly.
    • plasoc_axi4_full2lite.vhd --- Plasma-SoC's Slave AXI4-Full to Master AXI4-Lite Core.
    • plasoc_gpio.vhd --- GPIO Core.
    • plasoc_int.vhd --- Interrupt Controller.
    • plasoc_timer.vhd --- Timer Core.
    • plasoc_uart.vhd --- UART Core.
  • projects --- RTL examples.
    • Nexys4 --- Project developed specifically for the Digilent Nexys4 Artix-7 board.
    • VC707 --- Project developed specifically for the Xilinx VC707 Evalulation Kit.
• mips --- All the C/MIPs sources, including applications, drivers, and operating system.
  • apps --- Application that can run on the Plasma-SoC.
    • bootloader_app --- Currently supports loading an application into memory with in-circuit serial programming (ICSP).
    • cache_app --- Tests the operations of the CPU's L1 cache.
    • freertos_app --- Runs a FreeRTOS example.
    • threadmetric_apps --- Contains several applications needed to generate benchmarks for the Plasma-SoC FreeRTOS port with ThreadMetric.
    • timer_interrupt_app --- Tests the Time Core.
    • uart_app --- Tests the UART Core.
  • freertos --- FreeRTOS port for the Plasma-SoC.
  • plasma --- Sources related to Steve Rhoads' Plasma MLite Core. Note that boot source was modified for the purposes of the Plasma-SoC.
  • plasoc --- Sources needed for the Plasma-SoC. The drivers for the peripherals are located under this directory.
• misc --- All the utility programs.
  • bin2coe.py --- A command line program that generates either a COE file or a custom VHDL source that contains the HEX of a binary.
  • gencross.py --- A command line program that generates the wrapper for the crossbar interconnect.
  • icsp.py --- A command line program that loads a binary to the Plasma-SoC provided that the Plasma-SoC is running the bootloader.

• Cross compilation tools --- A GCC MIPS cross compiler and bin utilities are necessary to build binary. It is recommended to run this Makefile that downloads and builds the MIPS compiler and bin utilities. The Makefile has been tested on Ubuntu and Windows with Msys2. Alternatively, compilation and build tools can be immediately downloaded from uClib's download page, although these only work on Linux and are not fully updated.
• EDA --- The projects located under "hdl/projects/" are generated with Vivado. All of the testing up to this point has also been done with Xilinx's Vivado Design Suite IDE. However, the Plasma-SoC is developed for portability; it should run with any EDA or configurable logic development tools. It should be noted the version of Vivado used for development was 2016.4.
• Python2.7 --- In order to run the utility programs, a Python2.7 interpreter is needed. It is recommended to use Anaconda.
• PySerial --- The icsp.py command line utility program requires the PySerial module in order to operate.
• Serial Console --- In order to view messages from the UART Core, the host computer needs a serial console. The protocol is 9600 Baud 8N1. For Ubuntu, Minicom should already be installed. On Windows, Putty is recommended.

Applying the Plasma-SoC consists of setting up the RTL project with a selected EDA, compiling a binary for the hardware to execute, and deployment. These steps don't necessarily have to be completed in the order given.

All RTL development and testing so far been completed in Vivado 2016.4 IDE for the Digilent Nexys4 board and the Xilinx VC707 Evalulation Kit. With the IDE, a project can be generated by the following steps.

1. Start Vivado IDE.
2. In the TCL command line, use the "cd" command to change the directory to either "/hdl/projects/Nexys4" or "/hdl/projects/VC707".
3. Under the tools menu, use "Run TCL script.." to run the create_project.tcl script located in the directory specified in the last step.

At this point, the simulator can be started to demonstrate an application and compilation can be started to generate a bit file that already has the bootloader loaded into BRAM. More documentation can be found in the sources themselves.

The applications located in the "mips/apps" directory all depend on Makefiles in order to perform operations, such as building a binary or loading the binary on to the hardware. In each Makefile it is important that the variables BIN_DIR and LD_DIR are set to the appropriate directorys containing the cross compiler and libraries, respectively. In some Makefiles, these variables are instead called MIPS_GCC_BIN and MIPS_GCC_LIB respectively. They're always located at the beginning of every Makefile, however.

The make commands are described as the following.

• bootloader_app
  • make all --- Builds the bootloader binary and generates a boot_pack.vhd, which contains the binary in HEX. Adding the DEBUG_MAKE=1 argument causes the build to generate several files useful for debugging.
  • make install --- Copies boot_pack.vhd into "/hdl/projects/Nexys4" and "/hdl/projects/VC707".
  • make jump_build --- Builds the jump binary and generates a jump_pack.vhd, which contains the binary in HEX. Adding the DEBUG_MAKE=1 argument causes the build to generate several files useful for debugging.
  • make jump_install --- Copies jump_pack.vhd into "/hdl/projects/Nexys4" and "/hdl/projects/VC707".
  • make clean --- Removes all built files from directory.
• cache_app, freertos_app, timer_interrupt_app, uart_app
  • make all --- Builds the application binary and generates a main_pack.vhd, which contains the binary in HEX. Adding the DEBUG_MAKE=1 argument causes the build to generate several files useful for debugging.
  • make install --- Copies main_pack.vhd into "/hdl/projects/Nexys4" and "/hdl/projects/VC707".
  • make launch --- Uploads the binary on to the hardware with ISCP. The SERIALPORT variable should be set to the serial port of the hardware.
  • make clean --- Removes all built files from directory.
• threadmetric_apps --- "make all" builds all the applications, and "make clean" removes all the built files. The majority of the other commands end with either _build or _launch. The former builds the application, whereas the latter uploads the binary on to the hardware with ISCP. The argument DEBUG_MAKE=1 can be used after either _build or all to generate debugging files. The prefixes related to the ThreadMetric benchmark applications are the following.
  • make tm_basic_processing_test
  • make tm_cooperative_scheduling_test --- PLEASE READ. In order to run this application properly, the configUSE_PREEMPTION needs to be set to 0 before building the binary. The flag is located in FreeRTOSConfig.h under "mips/freertos". Every other application requires this flag to be set to 1.
  • make tm_interrupt_preemption_processing_test
  • make tm_interrupt_processing_test
  • make tm_memory_allocation_test
  • make tm_message_processing_test
  • make tm_preemptive_scheduling_test

There's also a Makefile located in "hdl/projects/Nexys4" and "hdl/projects/VC707" that generates the crossbar wrapper.

Kaleb Barrett's MIPS GCC Cross Compiler Makefile
Steve Rhoads' Plasma Core
Peter Bennett's UART Core
Real Time Engineer's FreeRTOS
Express Logic's ThreadMetric Download
AMBA4 AXI Specification
Xilinx Vivado Design Suite 2016.4
PySerial

Author: Andrew Powell
Contact: [email protected]
Blog: www.powellprojectshowcase.com
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