Analog-Design-of-Dynamic-Comparator

This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Power / (fs*2ENOB).

1) PreAmp Stage:

The focus in the preamp design was to be fast, more than to have a very high gain, since the regenerative latch provides the huge gain.
The ideal current source & Mcx are used to provide the biasing for Mc (current mirror) so the overdrive voltage of Mc won’t take much of the headroom, while providing good gain & speed.

2) Regenerative Latch Stage:

Cc1 & Cc2 are coupling capacitors that can be used for offset cancellation & blocks the DC level from the Preamp stage.
The transmission gates cause the inputs & outputs of the back-to-back inverters to reset to VDD/2 during the latch-reset phase. This speeds up the regeneration during the latch-regenerating phase.

3) RS Latch Stage:

The RS latch stage is for the comparator to maintain the sampled & regenerated value when the latch output is reset.
The input-inverters of the RS latch block are sized to move the inverters’ switching threshold point such that an input of 0.9V (during latch-reset phase) is considered high, thus causing the output-inverters to maintain the received information.

Clocked Comparator

Ideally, How the switches & the coupling capacitors work:

During clk = 1:

   𝑉_𝐶𝑎𝑝 = 𝑉_𝐶𝑀  − 𝑉_𝐼𝑁  
   𝑉_𝑔 = 𝑉_𝐶𝑀

During clk = 0:

  𝑉_𝑔  =  𝑉_𝐶𝑎𝑝 + 𝑉_𝑅𝑒𝑓 = 𝑽_𝑪𝑴 − (𝑽_𝑰𝑵  − 𝑽_𝑹𝒆𝒇) 

𝑉_𝑔n  = 𝑽_𝑪𝑴 − (𝑽_𝑰𝑵n  − 𝑽_𝑹𝒆𝒇n) 

𝑉_𝑔p  = 𝑽_𝑪𝑴 − (𝑽_𝑰𝑵p  − 𝑽_𝑹𝒆𝒇p) 

𝑉in(to_Preamp)  =  𝑉_𝑔p - 𝑉_𝑔n  =  − (𝑽_𝑰𝑵p  − 𝑽_𝑹𝒆𝒇p) + (𝑽_𝑰𝑵n  − 𝑽_𝑹𝒆𝒇n) = 2 * (𝑽_𝑰𝑵n  − 𝑽_𝑹𝒆𝒇n)

Overdrive test:

Testbench:

In this test, We want to find the smallest difference between Vin_p & Vin_n that the Comparator can detect (give the right output value), & this tells us the resolution of this comparator at this frequency.

4-bit Differential Flash ADC:

Whole System Testbench:

References:

-> My project on google drive:
https://drive.google.com/drive/folders/1W9ip4MpMZNf3IQsoFQkhgg6QaUya4Yp4
-> EE288 Lecture Notes:
https://drive.google.com/drive/folders/12Qqfw_TX1i7dvVVYXksaSdHV4gth1OD5

-> Check our paper:
M. Aldacher, M. Nasrollahpour, S. Hamedi-Hagh, “A low-power, high-resolution, 1 GHz differential comparator with low-offset and low-kickback”, 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Year: 2017, Pages: 310 – 313.

-> Video: "How Clocked Comparators work?"
https://www.youtube.com/watch?v=u1_9_BL5NjI

muhammadaldacher / analog-design-of-dynamic-comparator Goto Github PK