kuanwoo Goto Github PK

-greedy-guess-and-test-method-for-construction-qc-ldpc-codes-with-cpm-of-weigth-more-than-1.

Greedy Guess-and-Test method for construction QC-LDPC codes with CPM of weigth more than 1.

-tail-biting-spatially-coupled-qc-ldpc-codes-cycles-broken

Broke cycles according to shifts of tailbiting convolutional codes

5g-ldpc

5g ldpc codes

5g-polar-code

5g polar code

802.11ad-phy-sim

The repository contains the MATLAB-based model of IEEE 802.11ad physical layer in baseband.

802.11ah-af-phy-sim

This repository contains the baseband model of the IEEE 802.11ad and IEEE 802.11ah physical layer (PHY) simulators created in MATLAB.

802.11ay-phy-sim

adv_dbg_if

Advanced Debug Interface

aff3ct

A fast simulator and a library dedicated to the channel coding.

ajardsp

Automatically exported from code.google.com/p/ajardsp

algebraic_qc-ldpc

Algebraic methods for construction QC-LDPC

analog-design-of-1.5-bit-pipeline-adc-and-boosted-opamp

This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.

analog-design-of-1.9-ghz-pll-system

This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.

analog-design-of-10-gbasekr-high-speed-serial-link-transceiver-in-65-nm-cmos

This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.

analog-design-of-4-bit-current-steering-dacs

This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using high-swing cascode current mirror structures for the current source arrays.

analog-design-of-asynchronous-sar-adc

This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.

analog-design-of-bootstrapped-switch

This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A comparison is done between several topologies, showing the ENOB, SNR, & SFDR achieved in each case.

analog-design-of-dynamic-comparator

This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Power / (fs*2ENOB).

apb2per

apb_event_unit

apb_fll_if

apb_gpio

apb_i2c

apb_node

apb_pulpino

apb_spi_master

apb_timer

apb_uart

apb_uart_sv

ariane

Ariane is a 6-stage RISC-V CPU capable of booting Linux