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Salam, I'm Muhammad Aldacher 👋

📫 How to reach me: Linkedin

-> [ Study Material ]
-> [ Projects ]
-> [ MSc Courses (SJSU) ]


Study Material

Here, I will try to organize a study roadmap for people interested in Analog & Mixed-Signal design, based on my experience & what I studied before:

  1. Analog Design Basics
  2. Digital Circuits Basics
  3. PLLs (Phase-Locked Loops)
  4. ADCs (Analog/Digital Converters)
  5. LDOs (Low-Dropout Regulators)
  6. RF receiver system
  7. IO/SERDES system
    ..................................................................................

Projects

Project Category Year
1 8-bit Asynchronous SAR ADC design ADC Design 2020
2 1.5-bit Pipeline ADC with Boosted OpAmp ADC Design 2018
3 Dynamic Comparator design ADC design 2018
4 Bootstrapped Switch design ADC design 2018
5 Current-steering DAC design ADC design 2018
6 Modeling of 4-bit Flash ADC & DAC ADC design 2018
7 Modeling of 10-bit Pipeline ADC & DAC ADC design 2018
8 1.9-GHz PLL design PLL Design 2018
9 LDO Regulator design LDO Design 2018
10 1.9-GHz-Rx-frontend blocks RF design 2018
11 2.4-GHz LNA design RF design 2016
12 Transceiver for 10GbaseKR standard IO design 2013
13 8x8 SRAM array design Layout 2017
14 8-bit Microprocessor Layout 2013
15 FPGA Design of a Digital/Analog Clock Display FPGA 2017
16 DTFT & Convolution Signal Processing 2020
17 Z Transform & Tone Reduction Signal Processing 2020

MSc Courses (SJSU)

Course Year Semester
1 EE223 - Analog ICs Design 2016 Fall
2 EE220 - Radio Frequency Integrated Circuits Design I 2016 Fall
3 EE178 - Digital Design with FPGA 2017 Fall
4 EE224 - High Speed CMOS 2017 Fall
5 EE288 - Data Conversion for AMS ICs 2018 Spring
6 EE295 - Technical Writing 2018 Spring
7 EE230 - Radio Frequency Integrated Circuits Design II 2018 Fall
8 EE250 - Probability 2019 Fall
9 EE210 - LinearSystems 2020 Fall

Muhammad Aldacher's Projects

analog-design-of-1.9-ghz-pll-system icon analog-design-of-1.9-ghz-pll-system

This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.

analog-design-of-4-bit-current-steering-dacs icon analog-design-of-4-bit-current-steering-dacs

This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using high-swing cascode current mirror structures for the current source arrays.

analog-design-of-asynchronous-sar-adc icon analog-design-of-asynchronous-sar-adc

This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.

analog-design-of-bootstrapped-switch icon analog-design-of-bootstrapped-switch

This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A comparison is done between several topologies, showing the ENOB, SNR, & SFDR achieved in each case.

analog-design-of-dynamic-comparator icon analog-design-of-dynamic-comparator

This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Power / (fs*2ENOB).

layout-design-for-an-8-bit-microprocessor icon layout-design-for-an-8-bit-microprocessor

Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS VLSI technology on Tanner EDA toolchain.

layout-design-of-an-8x8-sram-array icon layout-design-of-an-8x8-sram-array

The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE, & the Static Noise Margin is obtained through Matlab scripts.

modeling-of-10-bit-pipeline-adc-and-10-bit-dac icon modeling-of-10-bit-pipeline-adc-and-10-bit-dac

This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pipelined architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.

modeling-of-4-bit-flash-adc-and-4-bit-dac icon modeling-of-4-bit-flash-adc-and-4-bit-dac

This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 4-bit ADC based on the flash architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.

rf-design-of-2.4-ghz-lna icon rf-design-of-2.4-ghz-lna

This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.

signal-processing-dtft-and-convolution icon signal-processing-dtft-and-convolution

This project is about designing generalized MATLAB codes that perform discrete convolution and discrete-time Fourier transform (DTFT) to audio and voice signals. Signal-processing MATLAB functions like “conv”, “filter”, and “fir1” are used to manipulate the input voice signal with different filters and study the output spectrum.

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