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mipt-mips's Introduction

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MIPT-V / MIPT-MIPS

MIPT-V / MIPT-MIPS is a pre-silicon simulator of MIPS and RISC-V CPU. It measures performance of program running on CPU, thus taking best features of RTL and common functional simulation:

  • Precision. We provide cycle-accurate models of branch prediction unit, pipeline, and other hardware internals.
  • Customization. Cache size, branch prediction algorithms, and other parameters can be easily changed even to unfeasible modes.
  • Simplicity. Our source files are much more readable than RTL and independent on SDK and synthesis flow.
  • Speed. 2 MHz simulation frequency on Cascade Lake.
  • Scalability. Modularized structure allows integration of more microarchitecture configurations.

Simulator can be used for different purposes:

  • Performance control of software optimizations: you may check what and why happened to IPC.
  • Pathfinding of hardware optimizations: you may easily integrate some nice feature to CPU model.
  • Comparison of hardware solutions from different vendors.
  • Performance control of developed or produced hardware.
  • Education: simulator is a nice experimental frog to study CPU internals and software development process.

Key system-level features:

  • Compatibility with interactive MARS system calls.
  • Interactive simulation with GDB

Key microarchitecture features:

  • Configurable branch prediction unit with several prediction algorithms
  • Configurable instruction cache
  • Interstage data bypassing

Topology visualization:

Topology

Pipeline diagrams:

Pipeline

More details about internals are available on Wiki.

For questions, use our Discussions page.

Requirements

We use C++20 features and Boost 1.71. Thus, you have to use compilers of these versions or newer:

  • GCC 11
  • Clang 13.0.0
  • Apple LLVM Version 13.1.6
  • MS Visual Studio 2019 16.8

Install Boost before building the project.

To work with RISC-V traces, you need to install RISC-V toolchain. Please follow the official instruction.

To work with MIPS traces, you need to install MIPS binutils. Please follow our manual if you are using Linux, OS X, or Windows.

Our build system is CMake. You should install CMake 3.13.5 or higher. Check our Wiki page to get more details about CMake. Users of IDE (Visual Studio, Eclipse, CodeBlocks etc.) may generate project files with CMake as well.

To generate RISC-V opcodes, CMake uses Python. python3 interpreter should be available in your environment.

Command line options

Standalone run options

  • -b <filename> — provide path to ELF binary file to execute.
  • -n <number> — number of instructions to run. If omitted, simulation continues until halting system call or jump to null is executed.

ISA and system-level options:

  • -I — modeled ISA. Default version is mars.
    • mips32, mips64 — state-of-the-art MIPS
    • riscv32, riscv64, riscv128 — RISC-V with all instructions
    • spim, spim64 — simplified MIPS without delayed branches
    • mipsI, mipsII, mipsIII, mipsIV — legacy MIPS versions
  • -f — enables functional simulation only
  • --mars — enables MARS-compatible mode of system calls

Outputs

  • -l — enables per-module output, for instance:
    • -l fetch,decode — prints only fetch and decode stages
    • -l cpu — prints all stages
    • -l cpu,!mem — print all except mem stage
  • -d — enables output of functional simulator
  • --tdump — enables module topology dump into topology.json

Performance mode options

Branch prediction

  • --bp-mode — prediction mode. Check supported modes in manual
  • --bp-lru — prediction replacement policy: LRU, pseudo-LRU, or infinite
  • --bp-size — branch prediction cache size (amount of tracked branch instructions)
  • --bp-ways — # of ways in branch prediction cache

Instruction cache

  • --icache-type — instruction cache type: LRU, pseudo-LRU, always-hit, or infinite
  • --icache-size — instruction cache size in bytes
  • --icache-ways — # of ways in instruction cache
  • --icache-line-size — line size of instruction cache

Execution pipeline

  • --long-alu-latency - number of execution stages required for long arithmetic instructions to be complete

Workflow example

Clone

  1. Check that your environment meets all the requirements above.
  2. Clone repository with submodules: git clone --recursive https://github.com/MIPT-ILab/mipt-mips.git

Build

To build simulator faster, we recommend to install Ninja.

  1. Create a new build directory somewhere, then cd into it: mkdir /path/to/your/build/directory
  2. Go to the build directory: cd /path/to/your/build/directory
  3. Run cmake /path/to/mipt-mips/simulator -G "Ninja" to configure CMake
  4. Run ninja to get the mipt-mips binary file
  5. If you changed some source code files, just type ninja to rebuild project

Run

  1. Now you can run simulation: ./mipt-mips -b /path/to/binary
  2. See more command line options in the paragraph below
  3. To run all unit tests, call ninja unit-tests && ctest --verbose -C Release from your build directory.

Test Coverage Chart!

Code Coverage

About MIPT-V / MIPT-MIPS

Logo

This project is a part of ILab activity at Moscow Institute of Physics and Technology (MIPT).

The main goal of the project is to teach the students the computer architecture through development of a microprocessor implementing the RISC-V and MIPS instruction set in both functional and performance simulators.

May I contribute?

Yes, if you attend lectures on Computer Architecture. See our contributing.md file for details.

mipt-mips's People

Contributors

agrachiv avatar alex19999 avatar alexander-titov avatar alexseppar avatar andreizoltan avatar beanefit avatar bova-ev avatar dandyforever avatar davtyan-arsen avatar denislos avatar dependabot[bot] avatar exucutional avatar gkorepanov avatar graudtv avatar igorsmir-ilab avatar inedostoev avatar ivan23kor avatar kiraproger avatar kkorolev avatar kkorolev-intel avatar kurapov-peter avatar olegladin avatar pavelkryukov avatar pooh64 avatar soshink avatar timofeevalex avatar trexxet avatar viktor-prutyanov avatar vodogrey2012 avatar yanlogovskiy avatar

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mipt-mips's Issues

Implement data bypassing

You have to introduce DataBypass class which will allow to perform bypassing between different pipe stages. The implementation should be close to scoreboard (producers mark registers as bypassible, consumers check if their registers are bypassible).

AMB: DataBypass class is fully connected to MIPT-MIPS and enabled in testing.

Introduce new types for cycles and latencies

Currently we use uint64 for accounting cycles. We may add better types with operator overloading, so some operations would be prohibited (like adding cycles to cycles).

Valid operations:

Cycle + Latency => Cycle
Cycle - Latency => Cycle
Cycle - Cycle => Latency
Cycle (compare) Cycle => bool
Latency + Latency => Latency
Latency - Latency => Latency
Latency / int => latency
Latency * int => Latency
int * Latency => Latency
Cycle % int => int

Examples of invalid operations:

Cycle * (anything)
Cycle / (anything)
Latency - Cycle

Both types should support literals.

Add wrong code detector in functional simulator

For the most of cases, execution of several (>10) sll $0, $0, 0x0 instructions means that program is executed incorrectly. We need to have an automized detector of such instructions in FuncSim to stop simulation if such sequence is detected.

Move all unit tests to single file

Historically assignments were about creation a tool and a unit test for it. However, now we can put all unit tests to the single unit, so they can be by single command.

Enhance register file with LO and HI registers

MIPS ISA defines LO and HI registers with implicit access by following instructions:

  • mult
  • multu
  • div
  • divu
  • mfhi
  • mthi
  • mflo
  • mtlo

MIPS restricts LO and HI usage to simplify dependency tracking (thus you have to track them as single register)

A computed result written to the HI/LO pair by DIV, DIVU,MULT, or MULTU must be read by MFHI or MFLO before a new result can be written into either HI or LO. If an MTHI instruction is executed following one of these arithmetic instructions, but before an MFLO or MFHI instruction, the contents of LO are UNPREDICTABLE. The following example shows this illegal situation:

 MUL       r2,r4   # start operation that will eventually write to HI,LO
 ...               # code not containing mfhi or mflo
 MTHI      r6
 ...               # code not containing mflo
                   # this mflo would get an UNPREDICTABLE value
 MFLO      r3

Example to reproduce:

$ ./perf_sim -b ../tests/samples/factorial.out -n 1300 -d
wb      cycle 147:bubble
decode  cycle 147:bubble
fetch   cycle 147:bubble
execute cycle 147:bubble
memory  cycle 147:mflo $t3, $zero, $zero	 [ $t3 = 0x0]
Executed instructions: 69

wb      cycle 148:mflo $t3, $zero, $zero	 [ $t3 = 0x0]
****************************
Mismatch: 
Checker output: mflo $t3, $zero, $zero	 [ $t3 = 0x1]
PerfSim output: mflo $t3, $zero, $zero	 [ $t3 = 0x0]

Support Windows-Ubuntu build

AMB: Make MIPT-MIPS fully buildable with Windows-Ubuntu. Manual to install required dependencies is published on Wiki.

Factorial trace (func_sim and perf_sim mismatch)

After fixing #73 I get

$ ./perf_sim -b ../tests/samples/factorial.out -n 1300 -d
wb      cycle 147:bubble
decode  cycle 147:bubble
fetch   cycle 147:bubble
execute cycle 147:bubble
memory  cycle 147:mflo $t3, $zero, $zero	 [ $t3 = 0x0]
Executed instructions: 69

wb      cycle 148:mflo $t3, $zero, $zero	 [ $t3 = 0x0]
****************************
Mismatch: 
Checker output: mflo $t3, $zero, $zero	 [ $t3 = 0x1]
PerfSim output: mflo $t3, $zero, $zero	 [ $t3 = 0x0]

Create option to select dumping units

There are two options at the moment: either all units do dump or none of them. The idea is to provide string name to each unit ("bp", "datacache" etc.) and enable their dump from command line. It should be implemented by combination of Log and Config classes.

Create option to select dumping units

There are two options at the moment: either all units do dump or none of them. The idea is to provide string name to each unit ("bp", "datacache" etc.) and enable their dump from command line:
./mipt-mips -units_log bp,datacache,fetch.

To implement this, Module class (#357) should be coupled with existing Log class, and Valuestd::string object.

Fix factorial.out

Problem with Factorial program.

To reproduce:

mipt-mips/tests/samples$ make build_all
mipt-mips/perf_sim$./perf_sim ../tests/samples/factorial.out 100 -d

Error message:

Executed instructions: 5

    fetch	cycle 15:  0x23bdfff4
    decode	cycle 15:  bubble
    execute	cycle 15:  or $t0, $v0, $zero	 [ $t0 = 0x4]
    memory	cycle 15:  syscall
ERROR: Writing to valid register!

Generate and test MS Visual Studio solution & project files with CMake

AMB: make MIPT-MIPS fully buildable with MSVS. Add a wiki manual if there are some tricks.

I've added MSVC command line build to AppVeyor with two noted

  1. I have to use patched LibELF build as original source contains a small bug
  2. MIPS binutils are built only by MinGW — it is OK as we use only binaries

Besides, everything is OK to create *.sln and *.vcxproj files (NMake is very, very bad)

Add deadlock detector

Currently deadlocks are not handled, simulator gets into an infinite loop. There should be a very simple handler — if there are no writebacks in previous 1000 cycles, error message is printed.

Fix factorial trace (Funcsim)

Currently factorial fails on instruction 62:

./perf_sim -b ../tests/samples/factorial.out -n 100 -d -f

jr $ra
perf_sim: ../func_sim/func_memory/func_memory.cpp:79: uint64 FuncMemory::read(uint64, short unsigned int) const: Assertion `check( addr)' failed.

The problem is that jal istruction does not perform writeback to $ra register.

Create a trace to test BP (not a bubble sort)

Currently no testing for Branch Prediction is made. We have to add the trace with huge amount of random branches.

The candidate was a bubble sort, but unfortunately, it is has low sensitivity to branch prediction.

AMB: Trace is implemented and shows sensitivity to BP mode.

Compare PerfSim and FuncSim internally

Currently we run PerfSim and FuncSim independently and then compare logs. However, if FuncSim was started inside PerfSim, we may get results a little bit simpler and faster.

Add self-modifying code stress test trace

MIPT-MIPS cannot model self-modifying code at the moment. However, at least we have to add some tests for that.
AMB: trace is added and demonstrates different behavior on Functional and Performance simulation

Enable very strict C++ warning rules

I personally prefer to enable as much C++ warnings as it is possible with -Wall -Wextra -Werror flags. Can someone please enable these flag and fix warnings appeared?

AMB: These flags are enabled in all Makefiles, all builds pass.

Build fails for some files

In func_instr:

$ make
g++-6 -std=c++14 -Wall -Wextra -Werror -O3 -c ../../func_sim/func_memory/func_memory.cpp -I ../../
g++-6 -std=c++14 -Wall -Wextra -Werror -O3 -MM -o  func_memory.d ../../func_sim/func_memory/func_memory.cpp -I ../../
g++-6 -std=c++14 -Wall -Wextra -Werror -O3 -c ../../func_sim/elf_parser/elf_parser.cpp -I ../../
g++-6 -std=c++14 -Wall -Wextra -Werror -O3 -MM -o  elf_parser.d ../../func_sim/elf_parser/elf_parser.cpp -I ../../
g++-6 -std=c++14 -Wall -Wextra -Werror -O3 -c disasm.cpp -I ../../
disasm.cpp: In function 'int main(int, char**)':
disasm.cpp:30:47: error: cannot convert 'std::__cxx11::string {aka std::__cxx11::basic_string<char>}' to 'const char*' for argument '1' to 'int strcmp(const char*, const char*)'
         if ( !strcmp( section[i].name, argv[2]))
                                               ^

In perf_sim:

 $ make
[g++-6] elf_parser.o
[g++-6] func_memory.o
[g++-6] func_instr.o
[g++-6] perf_sim.o
perf_sim.cpp:15:14: error: 'uint' does not name a type
 static const uint PORT_BW = 1;
              ^~~~

Merge ElfParser and Disassembler

Currently ElfParser and Disassembler do the same job of printin contents of MIPS binary file. The tools should be merged to one tool which prints both data and disassembled instructions.

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