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yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
Home Page: http://www.edaplayground.com/x/3qTu
License: GNU Lesser General Public License v3.0
SystemVerilog 97.97%
Makefile 1.00%
Python 1.03%
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on a 32-bit bus:
burst_type=e_FIXED
burst_size=e_2BYTES
addr='h21
len='1c
only bytelane 1 is used on 2nd-through beats instead of 0 and 1.
A couple silly copy/paste errors borked pipelined transfers. Thisis now fixed in a local sandbox but creating this bug to remind myself.
Make it easier for the test to set these.
It is entirely possible to randomly set ready and valid and have them not overlap, which hangs the sim because data never sends.
calculate beats returns an 8 bit vector.