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mk1057493329's Projects

ardupilot_wiki icon ardupilot_wiki

Repository for Ardupilot wiki issues and wiki-specific website infrastructure.

async_fifo icon async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

axi icon axi

AXI4 and AXI4-Lite interface definitions and testbench utilities

axi-uvm icon axi-uvm

yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/

basejump_stl icon basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

basic-simd-processor-verilog-tutorial icon basic-simd-processor-verilog-tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

cep icon cep

The Common Evaluation Platform (CEP) is an Open Source Hardware (OSH) System on a Chip (SoC)

cores icon cores

Various HDL (Verilog) IP Cores

deep-learning-books icon deep-learning-books

Books for machine learning, deep learning, math, NLP, CV, RL, etc. 一些机器学习、深度学习等相关话题的书籍。

dma icon dma

Open-Source AXI4 DMA Engine in SystemVerilog and Chisel

dpll icon dpll

A collection of phase locked loop (PLL) related projects

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