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License: MIT License
Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
License: MIT License
OriginalInput
module AOI (input A, B, C, D, output F);
assign F = ~((A & B) | (C & D));
endmodule
Output from test_bison.cpp
////////////// test1 ////////////////
VerilogDataBase::VerilogDataBase
ultrasimple.v:2.13-17: syntax error, unexpected INPUT, expecting NAME or ')'
////////////// test2 ////////////////
VerilogDataBase::VerilogDataBase
ultrasimple.v:2.13-17: syntax error, unexpected INPUT, expecting NAME or ')'
However, if we change it to:
module AOI (A, B, C, D, F);
input A;
output F;
assign F = ~((A & B) | (C & D));
endmodule
Then it succeeds (kind of). Not sure why it's reporting this error:
////////////// test1 ////////////////
VerilogDataBase::VerilogDataBase
verilog_module_declaration_cbk => AOI
A[-2147483648:-2147483648] B[-2147483648:-2147483648] C[-2147483648:-2147483648] D[-2147483648:-2147483648] F[-2147483648:-2147483648]
verilog_pin_declare_cbk => A 1 (-2147483648, -2147483648)
verilog_pin_declare_cbk => F 2 (-2147483648, -2147483648)
ultrasimple.v:5.15: syntax error, unexpected $undefined, expecting NAME
////////////// test2 ////////////////
VerilogDataBase::VerilogDataBase
verilog_module_declaration_cbk => AOI
A[-2147483648:-2147483648] B[-2147483648:-2147483648] C[-2147483648:-2147483648] D[-2147483648:-2147483648] F[-2147483648:-2147483648]
verilog_pin_declare_cbk => A 1 (-2147483648, -2147483648)
verilog_pin_declare_cbk => F 2 (-2147483648, -2147483648)
ultrasimple.v:5.15: syntax error, unexpected $undefined, expecting NAME
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