zhanghongce Goto Github PK

abc

ABC: System for Sequential Logic Synthesis and Formal Verification

aeval

AE-solver and Skolemizer

async

btor2verilog

Hacked together program to convert btor2 files to Verilog.

bypy

Python client for Baidu Yun (Personal Cloud Storage) 百度云/百度网盘Python客户端

cosa2

Next generation cosa.

cuda-code-samples

Source code examples from the Parallel Forall Blog

degpolytopeh

Finding H-representation of a (possibly degenerate) polytope given vertices

eda-wiki

EDA wiki

envsynsamples

Samples for Env. Inv. Synthesis

facetaxiomsublimesyntaxhighlight

The Syntax Highlight I used for Sublime for Facet Axiom used in ILA-MCM

garnet

garnet used in project

hwmcc19-in-chc

Benchmark from Hardware Model Checking Competition 2019, translated into CHC and VMT

ic3ref

IC3 reference implementation: a short, simple, fairly competitive implementation of IC3. Read it, tune it, extend it, play with it.

ila-mcm-fmcad18

ila-tools

A Modeling and Verification Platform for SoCs using ILAs

ila_aes

ila_flute

ila_piccolo

ILA modeling and verification of Piccolo RV32IU

ila_ridecore

ila_rocket

ilang-doc

ILAng documentation

inv-syn-examples

Examples for Invariant Synthesis

logo

mcm-smtlib2

SMT Encoding for SC & TSO (in SMT-LIB2 format)

mics6000h-prj2

mustool

pdr-prototype-tests

Testing different ideas with PDR

pysmt

pySMT: A library for SMT formulae manipulation and solving

pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL