Comments (8)
bmx
commented on June 17, 2024
Who's wrong? the datasheet? the linkutility?
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cnlohr
commented on June 17, 2024
Through invocation of the blackest dark magic I've ever seen, flash cells become RAM cells, and their sum is a constant.
wat
Can you validate the actual performance?
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maxgerhardt
commented on June 17, 2024
Who's wrong? the datasheet? the linkutility?
Ah, indeed I'm wrong, or rather, confusingly worded: The V30x devices marked "256K Flash + 64K SRAM" parts are actually configurable for the 4 options shown in the link utility. This is only the CH32V307(RC/WC/VC) and CH32V303(RC/VC) chips. For the other chips, 303(CB,RB), 305(FB,RB), they do have 128K flash and 32K RAM fixed.
CH32V307DS0.pdf:
For V20x series chips, only V203RB and all V208 have configurable sizes from selections, all others are 32K+10K or 64K+20K.
The point still stands however, V30x sreies chips can actually have 5 different configurations, the .ld file makes only 2 possible.
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cnlohr
commented on June 17, 2024
@dwillmore has been postulating that the flash is in fact RAM, and that it's somewhat arbitrary how it's configured. I am extremely curious if we find something like that. It seems that there are bits in the option rom for configuring the bits, see FLASH_OBR
@maxgerhardt would you be up for adding to the .ld file to enable the other forms? Also, it seems you will need to flash the option bytes in order to select between the different modes. Do you have any recommendations on how we could select the appropriate split?
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cnlohr
commented on June 17, 2024
Wait... does that mean it can be configured at runtime? I also see it here:
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jnk0le
commented on June 17, 2024
Through invocation of the blackest dark magic I've ever seen, flash cells become RAM cells, and their sum is a constant.
wat
@dwillmore has been postulating that the flash is in fact RAM, and that it's somewhat arbitrary how it's configured
This flash is in fact a sram loaded with image from "external" flash, typically done like this: htps://zeptobars.com/en/read/GD32F103CBT6-mcm-serial-flash-Giga-Devices
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dwillmore
commented on June 17, 2024
That's a different chip. But I was wondering if they were doing something
similar.
…On Mon, Apr 22, 2024, 2:30 PM jnk0le ***@***.***> wrote:
Through invocation of the blackest dark magic I've ever seen, flash cells
become RAM cells, and their sum is a constant.
wat
@dwillmore <https://github.com/dwillmore> has been postulating that the
flash is in fact RAM, and that it's somewhat arbitrary how it's configured
This flash is in fact a sram loaded with image from "external" flash:
htps://zeptobars.com/en/read/GD32F103CBT6-mcm-serial-flash-Giga-Devices
<https://zeptobars.com/en/read/GD32F103CBT6-mcm-serial-flash-Giga-Devices>
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jnk0le
commented on June 17, 2024
someone already decapped it https://cpldcpu.wordpress.com/2024/05/01/decapsulating-the-ch32v203-reveals-a-separate-flash-die/
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Related Issues (20)
- Make semihosting printf speed along if it times out.
- Empty LD file on missing build tools HOT 2
- prebuilt blink.bin example doesn't seem to work on a CH32V003 board HOT 4
- PWM 8 KHz 16 bit HOT 11
- Onewire slave
- CH32V003A4M6 SPI? HOT 2
- Is this board right for me? HOT 5
- Are there defined symbolic constants for AFIO_EXTICR register values? HOT 5
- minichlink not detecting esp32 programmer on MacOS. HOT 1
- DISCUSSION - Could this run Klipper ? I think it really could omg HOT 8
- Why does my code stop when I connect minichlink terminal? HOT 8
- v30x blink example don't run if TARGET_MCU_PACKAGE sets to CH32V307VCT6 HOT 6
- General Cleanup
- Funny bug in startup HOT 6
- "stdio.h" file not found HOT 5
- how to reset/reboot the chip when flash done via minichlink? HOT 2
- USART example is empty HOT 2
- Support for new CH32V006 / CH32V005 boards? HOT 2
- How do you write the userdata flash from the bootloader? HOT 1
- How to use GPIO_digitalWrite_branching ? HOT 2
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