I am trying to run 3 PWM on TIM1 (to control a common anode RGB LED), but i am confused by something :
There is 4 OC channel, so normally we can run up to 4GPIOs on TIM1, however in the driver there is also only two channels here :
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// CH1 Mode is output, PWM1 (CC1S = 00, OC1M = 110) |
So, i was trying to add support for the channels i use, but i came here stuck since there is only two channels possible here.
What is the reason? does it mean we can only ever run two PWM channels maximum on TIM1?
On stm32 for example we can run 4 channels just with OC, so i dont get it.
Currently only the blue channel works (T1CH1) both the green and red stay off, probably floating otherwise the LED would be full ON (it is a common anode).
In my case i try to run these ports :
//R : PA2 T1CH2N
//G : PC6 T1CH3N
//B : PD2 T1CH1
and that is how i started to modify the init:
void t1pwm_init(void){
//R PA2 T1CH2N
//G PC6 T1CH3N
//B PD2 T1CH1
// Enable GPIOA, GPIOC, GPIOD and TIM1
RCC->APB2PCENR |= RCC_APB2Periph_GPIOA |
RCC_APB2Periph_GPIOD |
RCC_APB2Periph_GPIOC |
RCC_APB2Periph_TIM1;
// PD0 is T1CH1N, 50MHz Output PP CNF = 10: Mux PP, MODE = 11: Out 50MHz
//GPIOD->CFGLR &= ~(GPIO_CFGLR_MODE0 | GPIO_CFGLR_CNF0);
//GPIOD->CFGLR |= GPIO_CFGLR_CNF0_1 | GPIO_CFGLR_MODE0_0 | GPIO_CFGLR_MODE0_1;
// PC4 is T1CH4, 50MHz Output PP CNF = 10: Mux PP, MODE = 11: Out 50MHz
//GPIOC->CFGLR &= ~(GPIO_CFGLR_MODE4 | GPIO_CFGLR_CNF4);
//GPIOC->CFGLR |= GPIO_CFGLR_CNF4_1 | GPIO_CFGLR_MODE4_0 | GPIO_CFGLR_MODE4_1;
// PD2 is T1CH1, 50MHz Output PP CNF = 10: Mux PP, MODE = 11: Out 50MHz
GPIOD->CFGLR &= ~(GPIO_CFGLR_MODE2 | GPIO_CFGLR_CNF2);
GPIOD->CFGLR |= GPIO_CFGLR_CNF2_1 | GPIO_CFGLR_MODE2_0 | GPIO_CFGLR_MODE2_1;
// PA2 is T1CH2N, 50MHz Output PP CNF = 10: Mux PP, MODE = 11: Out 50MHz
GPIOA->CFGLR &= ~(GPIO_CFGLR_MODE2 | GPIO_CFGLR_CNF2);
GPIOA->CFGLR |= GPIO_CFGLR_CNF2_1 | GPIO_CFGLR_MODE2_0 | GPIO_CFGLR_MODE2_1;
// PC6 is T1CH3N, 50MHz Output PP CNF = 10: Mux PP, MODE = 11: Out 50MHz
GPIOC->CFGLR &= ~(GPIO_CFGLR_MODE6 | GPIO_CFGLR_CNF6);
GPIOC->CFGLR |= GPIO_CFGLR_CNF6_1 | GPIO_CFGLR_MODE6_0 | GPIO_CFGLR_MODE6_1;
// Reset TIM1 to init all regs
RCC->APB2PRSTR |= RCC_APB2Periph_TIM1;
RCC->APB2PRSTR &= ~RCC_APB2Periph_TIM1;
// CTLR1: default is up, events generated, edge align
// SMCFGR: default clk input is CK_INT
// Prescaler
TIM1->PSC = 0x0000;
// Auto Reload - sets period
TIM1->ATRLR = 255;
// Reload immediately
TIM1->SWEVGR |= TIM_UG;
// Enable CH1N output, positive pol
//TIM1->CCER |= TIM_CC1NE | TIM_CC1NP;
// Enable CH4 output, positive pol
//TIM1->CCER |= TIM_CC4E | TIM_CC4P;
// Enable CH1 output, positive pol
TIM1->CCER |= TIM_CC1E | TIM_CC1P;
// Enable CH2N output, positive pol
TIM1->CCER |= TIM_CC2NE | TIM_CC2NP;
// Enable CH3N output, positive pol
TIM1->CCER |= TIM_CC3NE | TIM_CC3NP;
// CH1 Mode is output, PWM1 (CC1S = 00, OC1M = 110)
TIM1->CHCTLR1 |= TIM_OC1M_2 | TIM_OC1M_1;
// CH2 Mode is output, PWM1 (CC1S = 00, OC1M = 110)
TIM1->CHCTLR2 |= TIM_OC4M_2 | TIM_OC4M_1;
// Set the Capture Compare Register value to 50% initially
TIM1->CH1CVR = 128;
TIM1->CH2CVR = 128;
TIM1->CH3CVR = 128;
TIM1->CH4CVR = 128;
// Enable TIM1 outputs
TIM1->BDTR |= TIM_MOE;
// Enable TIM1
TIM1->CTLR1 |= TIM_CEN;
u32 count=0;
while(1)
{
t1pwm_setpw(0, count); // Ch 1
t1pwm_setpw(1, (count + 64)&255); // Ch 2
t1pwm_setpw(2, (count + 128)&255); // Ch 3
count++;
count &= 255;
Delay_Ms(5);
}
}