Comments (5)
Not sure what the best solution would be here. I don't think using signed_integer
is a good idea though - first, it isn't going to work as expected if byte_lanes
isn't 1 (and I think the bit masking is going to remove the sign information anyway even if you swap integer
for signed_integer
). Second, bytes
doesn't accept signed integers, you get an exception if there is anything outside of 0-255, at least when byte_size
is 8.
I'm thinking maybe the "right" solution would be to add a config option somewhere (probably to the constructor) to control sign bit handling in the RX direction. This would also force anything with 8 bit bytes to use list
instead of bytes
so the sign information is preserved.
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Thank you for the quick reply.
I am using byte_size=12
Could you please let me know how exactly to do it?
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And another issue, the input sample is around 80,000 and the output samples I receive using axistreamsink is 160,000(almost double ). Any idea where I might be wrong ?
But its right when i just use AXIStremSource to drive samples to dut and collect it using my own logic.(without sink)
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Wrong number of outputs makes me thing you're not implementing the AXI stream handshake correctly somehow. If your logic works when it's talking to another piece of your own logic, my guess is you may have misunderstood some aspect of the AXI stream spec. I would have to see a waveform dump to get to the bottom of whatever is going on.
Also, I suppose it might make sense to add some additional assertions, for example if tvalid is high but tready is low, no signals are allowed to change until tready goes high. This would probably help catch a few bugs.
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Also, to manually recreate the sign bit, I think the simplest thing to do is something like this, assuming your data bus is 16 bits wide (so the sign bit is bit 15):
data = [(x ^ 2**15) - 2**15 for x in data]
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Related Issues (20)
- 0.1.20 makes my tests fail HOT 43
- axi address width causing overflow HOT 5
- address may exeed signal width HOT 2
- Axi Streaming is missing support for tstrb
- Is the repo unmaintained / closed to new features? HOT 2
- AxiStreamSink cannot handle tdata X-bytes for bytes to ignore (tkeep=0) HOT 1
- Missing signal results in AssertionError During handling of the above exception, another exception occurred: HOT 5
- Axis DUT signal naming HOT 1
- manually set tlast=1 when sending the last sample HOT 4
- Something is broken between 0.1.20 and 0.1.22
- Conditional logging
- No support for suffixed AXI bus signal names
- AxiStreamSource shows unexpected behaviour with TUSER and multiple byte_lanes HOT 4
- Setting optional arguments arid,awid in AxiMaster don't seem to work
- Axi stream receiving 8b chunks when sending 32b data HOT 3
- Assigning value to individual signals of AXI Read Address Channel HOT 9
- Issue accessing AXI4Lite bus signals wrapped in a VHDL record HOT 2
- AxiStreamMonitor: Monitor AXIS in a hierarchy deeper than top dut HOT 1
- Writing to / Reading of AxiRam from the hardware DUT hang when adding when loops to the test bench
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