Comments (9)
What signals specifically do you want to set? You can influence quite a bit, but you can't arbitrarily set whatever you want.
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Yes, mainly address, length, size, cache, protection bits
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You should be able to set all of that when calling read(). Length and address will naturally be modified when the request is split up into bursts, but the other values should get passed through as is. What issue are you running in to, exactly?
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Thanks Alex!!
I am using your AXI IPs (Verilog AXI Components). And I would like to do only one request(either write or read).
Say, I am performing one write transaction, no read. Simulation resulting in successful pass but I am able to see unknown('x') when I view waveform under Read Channel Signals.
I want to avoid this. I need some help here.
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I am able to remove unknowns("x").
I wanted to pass length as an argument for tb.axi_master.write().
But, found that it throws TyperError: Unexpected keyword argument.
Can you guide me, any alternative I can follow?
Thanks Alex!!
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I think all of the signals aside from ready/valid are set to X initially. They will get changed when the first operation takes place. There has been some talk about setting everything to X whenever the valid signal is low, but it's not set up that way yet.
Are the Xs causing problems in your design somehow? In general, I think they should not be an issue so long as you're properly handling the ready/valid handshaking.
You can't specify a length for write operations as the length is derived from the write data. So just pass in however much data you want to write and the BFM will take care of the rest.
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Okay, I got it on handling X's.
So just pass in however much data you want to write , you mean I can write any number of bytes. (Ex : data = 128bytes)
Thanks Alex!!
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Yep. Just pass in whatever data you want to write as bytes or bytearray (or something that can be cast to bytes), and it will get split up and re-packed as necessary. If you want to pass in a list of 32 bit ints or something instead of bytes, then there are word access versions as well (write_dwords/read_dwords, etc.)
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Thanks Alex!!
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Related Issues (20)
- 0.1.20 makes my tests fail HOT 43
- axi address width causing overflow HOT 5
- address may exeed signal width HOT 2
- Axi Streaming is missing support for tstrb
- Is the repo unmaintained / closed to new features? HOT 2
- AxiStreamSink cannot handle tdata X-bytes for bytes to ignore (tkeep=0) HOT 1
- Missing signal results in AssertionError During handling of the above exception, another exception occurred: HOT 5
- Axis DUT signal naming HOT 1
- manually set tlast=1 when sending the last sample HOT 4
- Something is broken between 0.1.20 and 0.1.22
- AxiStreamSink not reading signed_int from dut HOT 5
- Conditional logging
- No support for suffixed AXI bus signal names
- AxiStreamSource shows unexpected behaviour with TUSER and multiple byte_lanes HOT 4
- Setting optional arguments arid,awid in AxiMaster don't seem to work
- Axi stream receiving 8b chunks when sending 32b data HOT 3
- Issue accessing AXI4Lite bus signals wrapped in a VHDL record HOT 2
- AxiStreamMonitor: Monitor AXIS in a hierarchy deeper than top dut HOT 1
- Writing to / Reading of AxiRam from the hardware DUT hang when adding when loops to the test bench
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