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Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

License: GNU General Public License v3.0

Verilog 71.91% C++ 28.09%

quickspi's Introduction

SPI Verilog modules 2 SPI implementations:

Fully Hard for FPGA without CPU core like Spartan 6 or Cyclone 4, e.t.c. features:
- setting bit (MSB, LSB) and bytes order (Little endian or Big endina)
- adjustable number of extra clocks when some devices needs to make internal synchronizzation while CS is still active and clock keep going from clk (Dragster/Awaiba/Cmosis DR-2k-7)
Fully soft SPI with AXI Full interface with CPU.

Сейчас посылки кратны 8 бит, но, возможно, для некоторых случаев необходимо посылать меньшее число байт, например 1 ниббл (4 бит) и т.п.

Необходимо настраивать следующие параметры:

Порядок следования бит в байте: LSB/MSB First.

Порядок следования байт в пачке байт

Размер пачки, передаваемых байт

Число используемых бит, т.е. хорошо бы задавать кратность данных в битах, а не в байтах.

Необходимо продумать и предложить каким должен быть интерфейс QuickSPI для взаимодействия с другими модулями и процессоорным ядром.

Необходимо разделить большое состояние ACTIVE на несколько состояний, или же для этого использовать функции или таски.

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