tejeez / geckokapula Goto Github PK

Good afternoon, your project is very interesting for me, I’m trying to do something similar, but on the Efr32XG28 it seems to be more powerful and the processor is faster. can you answer a few questions? 1. Is your firmware suitable for Efr32XG28? 2. how did you defeat resetting the frequency in a wide range, without reloading the configuration for different frequencies. which configurator do you use, silabs studio does not allow you to set the "actual sample frequency" parameter and my DMA works at the maximum frequency and the processor choke

Hi!
I'm one of the founders and developers of the OpenRTX project (https://openrtx.org/) and I just found this project: it looks like a perfect match for our work, are you interested in a cooperation?

73,
Silvano IU2KWO.

Some users might like to have a frequency divided reference clock available on some pin. The clock management unit (CMU) can output HFEXPCLK on CMU_CLK0 and CMU_CLK1. There's "CMU_HFEXPPRESC - High Frequency Export Clock Prescaler Register" with 5 bits, allowing division factors from 1 to 32.

CMU_CLK0 can be routed to PA1, PB15, PC6, PC11, PD9, PD14, PF2, PF7.
CMU_CLK1 can be routed to PA0, PB14, PC7, PC10, PD10, PD15, PF3 and PF6.
Out of these, the following pins exist on the EFR32FG14P233F256GM48:

• PA0, PA1 - reserved for UART, but not actually used at the moment
• PB14 - used (SPK_PWM)
• PB15 - used (VBAT_ADC)
• PC6, PC7, PC10, PC11 - used for display since version 1, so I'd rather not change these
• PD14, PF7 - used for buttons since they support EM4 wakeup. EM4 is not used for now but could be.
• PD15 - used (RX_EN)
• PF2, PF3 - reserved for SWO and JTAG
• PF6 - used (encoder)

So, which one should we use? Looks like PB14, PB15, PD15, PF6 could be moved somewhere else. That would need modifications to the existing prototypes but I think only 3 of those exist at the moment, so it wouldn't be that bad.

PF3 is "free" and available on a test pad. Does someone want to use JTAG, though?

PA0 and PA1 are already available on a header but the plan was to use that one for UART. UART could be routed to any other free pin, though.

Let's collect some ideas for the next batch of PCBs here.

I'd rather not maintain a separate firmware for v2 and v2.1, so it should be mostly pinout compatible with v2. If something is changed in the pinout, the existing v2 boards can be modified to work with latest firmware.

I decided to not focus that much on mechanical design yet, so I think v2.1 will just use the same enclosure and similar construction as v2.

List of some ideas:

• Fix enclosure mounting hole positions.
• Remove the BJT microphone preamplifier and try using the internal opamp in EFR32. This would reduce component count and allow adjusting microphone gain from the firmware. This should be tested first by modifying v2 boards.
• Should we still use ETC4-1-2 as the balun for EFR32 matching or find a replacement from JLCPCB?
• The class D audio output stage does not have proper filtering. I thought voice coil inductance of a speaker might be enough but haven't actually measured it. Some people, however, have added a headphone connector. How bad is it to continuously feed a ≈1 V 192 kHz tone to headphones?
• #2
• Make unfiltered RF signals easier to access. EFR32 can tune wider than expected so it would be nice to allow some experimentation. Maybe add some 0-ohm jumpers to bypass filters.
• How about replacing the 3.3 V LDO with a switching regulator for better battery life and less heat? The regulated voltage could be also reduced a bit (say, 3.0 V), so that it maintains regulation even with a bit less battery voltage.