Comments (1)
Basicaly, when SpinalHDL see that a component is using a clock domain, it pull all signals of this clock domain into the component (including reset, even if it's not required).
For SpinalHDL a clock domain is the clock + reset + clock enable signals, it isn't trying to ditch out things, as it doesn't realy matter.
The clock domain used by default is one with a clock and reset signal, so the easy way to get ride of the reset is to override the default clock domain with one which as only one clock signal
There is an example how to do that
object PlayDefaultClockDomain{
class Blink extends Component {
val io = new Bundle {
val led5 = out Bool
}
io.led5 := True
val count = Reg(UInt(21 bits))
count := count + 1
// io.led5 := count.msb
}
def main(args: Array[String]): Unit = {
SpinalVerilog(ClockDomain.external("", withReset = false)(new Blink))
}
}
from spinalhdl.
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